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  1. #1
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    vhdl srl

    when I use SRL,ROR,... operator in VHDL
    modelsim5.8sb shows

    # ** Error: ./rtl/SPI_Model.vhd(136): No feasible entries for infix op: "srl".
    # ** Error: ./rtl/SPI_Model.vhd(136): Type error resolving infix expression.
    # ** Error: ./rtl/SPI_Model.vhd(146): VHDL Compiler exiting
    # ** Error: C:/Modeltech_5.8b/win32/vcom failed.

    which package should I add,
    I have added

    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    use ieee.numeric_std.all;

    but failed

    •   Alt18th June 2004, 08:14

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  2. #2
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    vhdl shr

    there are not such operation in VHDL, i think

    what VHDL has in ieee.std_logic_arith is
    shl shr
    which can be use for signed or unsigned number

    and in ieee.numeric_bit

    there are shift_left/shift_right
    rotate_left/right

    regards



  3. #3
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    srl vhdl

    a reference book named "HDL Chip design" by Douglas J Smith
    page 69 contains SLL SRL operator example,but it contains
    ieee.numeric_std.all, I wondwr if the examples of the chapter
    are executable



  4. #4
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    vhdl ror

    Quote Originally Posted by gerade
    there are not such operation in VHDL, i think

    what VHDL has in ieee.std_logic_arith is
    shl shr
    which can be use for signed or unsigned number

    and in ieee.numeric_bit

    there are shift_left/shift_right
    rotate_left/right

    regards
    I did add this package but still shows the same message!
    What's wrong with my modelsim or something?



  5. #5
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    ror vhdl

    Code:
    use ieee.std_logic_arith.all; 
    use ieee.std_logic_unsigned.all; 
    use ieee.numeric_std.all;
    You include too many packages. All three packages are mutually exclusive. You should use numeric_std only, and have a look at the operators defined for numeric_std, in section 2 of
    http://www-lsi.die.upm.es/~marisa/docencia/1164pkg.pdf

    The VHDL spec says that if two different definitions are imported from packages, they destroy each other.



    •   Alt27th June 2004, 10:54

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  6. #6
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    vhdl srl example

    I add only
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.numeric_std.all;

    and founf`d the same condition , why?



  7. #7
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    shr vhdl

    Instead of all these difficulties...
    u can use simple logic like...

    if u want to do left shift.. then say ur signal is of 8 bit vectors.. and ur inoput is single bit then..

    outdatareg(7 downto 1) <= indatareg(6 downto 0);
    indatareg(0) <= indata;
    like this u can implement left or rigth shift opreations...

    jay



  8. #8
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    vhdl sll example

    Quote Originally Posted by jay_ec_engg
    Instead of all these difficulties...
    u can use simple logic like...

    if u want to do left shift.. then say ur signal is of 8 bit vectors.. and ur inoput is single bit then..

    outdatareg(7 downto 1) <= indatareg(6 downto 0);
    indatareg(0) <= indata;
    like this u can implement left or rigth shift opreations...

    jay
    I know it's not difficult to do that. but just curious such kind
    of common operator cannot be done, I never found similar
    problem in verilog. How can I love VHDL more?



  9. #9
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    vhdl sll

    Is it a problem of VHDL version? '87 or '93.. juz change the option and see.



  10. #10
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    sll vhdl

    Its problem of VHDL'93....
    ALTERA is not supporting all the features of IEEE93 standards.....
    u cant use some good fuinctions which they are saying " IT WILL WORK with 93 version"... dont know about xilinx or otehr tools

    jay



  11. #11
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    shl vhdl

    Roger,

    I think you're problem might be that you're not passing the SRL function a data type that it recognizes. I believe it only supports bit vectors. If you want to use a std_logic_vector you would have to do something like:

    to_stdlogicvector(to_bitvector(wrptr2) srl i)



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