[SOLVED] Powering Zigbee, WiFi, and GPS modules over FPC cable

I am designing a small PCB to serve as a daughtercard for a much larger PCB. The small PCB is connected to the larger PCB by a 50-pin FPC cable. The length of the FPC cable is 7 inches.

Zigbee, WiFi, and GPS modules will be mounted on the small PCB. There will be three modules in total, and the maximum current drain of all three modules is approximately 330 mA. All three modules are operated at 3.3V levels.

I think that there are three ways to adequately supply power to these three modules on the daughtercard:

(1) Power is supplied to the daughtercard over the FPC cable at a higher voltage of ~5V. A low-dropout linear regulator on the daughtercard provides a 3.3V rail to the three modules. A large decoupling capacitor of ~100uF is placed on the input rail of the daughtercard. Multiple pins of the FPC cable will be used for the input rail and GND.

(2) Power is supplied to the daughtercard over the FPC cable at a nominal 3.3V. The voltage drop due to the resistance of the cable is low since multiple pins are used for the input rail. A large decoupling capacitor of ~100uF is also placed on the input rail of the daughtercard.

(3) Power is supplied to the daughtercard in exactly the same way as the first scheme above, but a DC/DC switcher is used to step down the voltage from 5V to 3.3V.

Could anyone comment on which would be the best scheme? The first scheme (1) will have a higher power consumption due to the inefficiency of the linear regulators, but noise will be low. The second scheme (2) may suffer from voltage droop. The third scheme (3) may work well, but may have additional noise due to the DC/DC switcher. What works well in practice?

I'd recommend scheme (2). 330mA isn't too much for several parallel wires of such a short cable. Additionally use 10..100nF cercaps at the power supplies of each IC on board.

Sure, that sounds good to me, thank you for your recommendation. How many pins on the FPC cable should be used for this scheme? Perhaps >5 pins would be good?

nkinar said:

How many pins on the FPC cable should be used for this scheme? Perhaps >5 pins would be good?

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As many as you have left over (but keep a few spare wires, you later might need them ;-) ).

Such an FPC cable should own about 340µΩ/mm, or ≈120mΩ per wire pair (GND & VDD) @ 7" length, or ≈40mV voltage drop per wire pair @ 330mA, i.e. <10mV drop with 5 wire pairs. The contact resistance could prevail, however.

BTW: Use the VDD & GND wires as screens between your signal wires!

I think that I'll use this scheme; once again, thank you erikl!

My cable pinout is as follows:

Pins 1 to 7: Higher voltage (5.6V) rail for ADCs and op-amps, regulated down to 5V and 3.3V on the daughtercard by LDO linear regulators (ADP3303 from Analog Devices)
Pins 8 to 12: 3.3V rail for Zigbee, WiFi, and GPS modules, non-regulated
Pins 13 to 40: Signals, with GND wires between each signal pin (i.e signal, GND, signal, GND)
Pins 41 to 50: direct connection to GND plane

Should I pair VDD and GND wires between the signal wires, or would it suffice to only use GND between each signal pin?

This reminds me of a rather expensive mistake I made once (where there was audio circuitry on the daughter board). I had used the same connections&wires for all the 0volt requirements on the board. Mains hum was a permanent problem!
I should have used quite separate connections for power (incl. the decoupling caps), for 0v signal reference (used for all ground references and signal-related connections to ground) and for screening low level signals.
Just in case any of these apply to you, perhaps you could allocate one wire for 'clean' signal-related 0v and leave the others for power?
I agree that it is wise to place the 0v wires around the wires carrying any low-level signals.

Sure, thank you for your comments.

nkinar said:

Should I pair VDD and GND wires between the signal wires, or would it suffice to only use GND between each signal pin?

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I'd imagine that pairing VDD & GND around the signal lines would be clever, as anti-phase interferences on the power supply wires would mutually cancel their influence on the signal wire.

So: GND sig1 VDD sig2 GND sig3 VDD ...

Thanks again for your response, erikl; I'll go ahead with the scheme discussed in this thread. However, what happens when there is a split power rail such as the one discussed above, with 5.6V and 3.3V rails? Would I surround the signal wires with the 3.3V rail or with the 5.6V rail? All GND pins will be taken to a ground plane on the daughtercard.

Alternately, even if the 5.6V rail is regulated on the daughtercard, would I surround the signals with the power supply for the components that originate the signals?

That is

GND, sig1-3.3V, 3.3V, sig2-5.6V, GND

or

GND, sig1-3.3V, 3.3V, sig2-3.3V, GND, sig3-5.6V, 5.6V, sig4-5.6V, GND

I would be more inclined to perhaps use the second scheme.

nkinar said:

GND, sig1-3.3V, 3.3V, sig2-3.3V, GND, sig3-5.6V, 5.6V, sig4-5.6V, GND

I would be more inclined to perhaps use the second scheme.

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Yes, this is my opinion, too.

However :-( , for my above mentioned interference cancellation idea - in order to really work well - this would need separate GND-3.3V and GND-5.6V wires. It gets more & more complex! :-(

Thanks again, erikl. That's not too complex if there are separate ground planes for analog and digital sections of the PCB. I also think this would work better for multilayer PCBs, where the the routing would be much simpler.