[SOLVED] Digital Electronics Elementary Question 2

1. What will happen if Data & Clk pins of a D-flop is shorted and a clock is given as input?
2. We have an SRAM connected with a bus interface. How will we verify it,
a) assume addr bus of i/f [7:0] is connected to SRAM addr bus [0:7].
b) How effectively we can catch this bug.
c) How will be checking all the address locations
3. Design a circuit which will produce clock as output, and 2 inputs "str_clk" and "stp_clk". if "str_clk==1" then only clock should generate and if "stp_clk==1" output should be low (stoping clock).

1. Unknown if you violated the setup and hold times. you could get a 1, 0, runt pulse, toggle...anything goes.
2. walk ones/zeroes/patterns through the memory via writes, then read back and verify.
3. that's more complicated, but you should do it synchronously. if you are asking these "elementary" questions, you should stick to synchronous designs for now and not be starting and stopping clocks, but rather enabling or disabling pulses that you use the clock to sample.

Hi ipsips,
I didnt get any proper answer from you. I was expecting the answers, instead of another question.

-paulki

What's up with your ass attitude toward a person who spent time to asnwer your question ?
He answered right for Q1.
You can't catch such a bug with Q2. It's not even a bug functionally.
For the question 3, my only advice is use latch. you are not a newbie and if you at least try by yourself and show your effort, we might help you.

Hi lostinxlation,
You could've use better word to address a professional. Its not a problem to me.... I need the solution.
I dont know the answer for the questions which I posted, otherwise why this Forum itself required? I'm begging sorry to ipsips if the reply hurted him. I dint mentioned anybody spent time for the Qns, but I dint get the response.
If you know the answers why dint you post it, instead of bashing???
Correct me the assumptions made me if wrong.
1. Answer is "X" mostly, since D & Clk is shorted, only delay is clock to q (Tcq) cant serve the setup-hold time margins and timing violation can leads to the Output metastable.
2. a). Write a monitor which always returns the address as LITTLE ENDIAN or BIG ENDIAN fashion.
b). Write Address Wrap functions to identify such bugs (Memory Overflow conditions).
c). Walking 1's and 0's is enough to test. Or prefilled pattern will serve the purpose.
3. I couldnt realise in Verilog, that the reason I posted.

Appreciate and awaiting your answers.

-paulki

paulki said:

1. Answer is "X" mostly, since D & Clk is shorted, only delay is clock to q (Tcq) cant serve the setup-hold time margins and timing violation can leads to the Output metastable.

Click to expand...

Tcq is irrelevant. Shorting D and clk would end up in the setup or hold violation. If you have setup and hold window not around on the rise edge of the clock, it can work without getting X.

2. a). Write a monitor which always returns the address as LITTLE ENDIAN or BIG ENDIAN fashion.
b). Write Address Wrap functions to identify such bugs (Memory Overflow conditions).
c). Walking 1's and 0's is enough to test. Or prefilled pattern will serve the purpose.

Click to expand...

a. Works only on simulation. Endianness is something different.
b. If there are 256 entries, it won't overflow.

3. I couldnt realise in Verilog, that the reason I posted.

Click to expand...

Search clock gating cell on google.

Hi lostinxlation,
Appreciate your effort.
1. I'm eager to understand how "the setup-hold window not around the rise edge of the clock", if the Clk and D are shorted? In simulation it may work without X. Could you please explain in understandable form.
2. a). I can properly verify how the Address come L-Endian or Big-Endian by writing monitor which display.

Thanks,
Paul

paulki said:

Hi lostinxlation,
Appreciate your effort.
1. I'm eager to understand how "the setup-hold window not around the rise edge of the clock", if the Clk and D are shorted? In simulation it may work without X. Could you please explain in understandable form.

Click to expand...

It depends on the design of the flop. If CLK is delayed a LOT with respect to D inside the flop, setup/hold window moves later past the rise edge of the clock. In this case, if CLK and D are shorted and change at the same time, the flop will get 1.
If D is delayed a lot with respect to CLK inside the flop, setup/hold window moves early past the rise edge of the clock. In this case, if CLK and D are shorted and change at the same time, the flop will get 0.

paulki said:

Hi lostinxlation,
Appreciate your effort.
1. I'm eager to understand how "the setup-hold window not around the rise edge of the clock", if the Clk and D are shorted? In simulation it may work without X. Could you please explain in understandable form.

Click to expand...

In real word there won't be a 'x'. It may or may not go to metastable state depends on the kind of the flop.
In verilog simulation, if you are running no timing check option the you won't see a 'x' and the o/p depends on ur flop behavioral model.

If you question is on how to check these kind of problems? then two methods are there :
1) try to create a test scenario where u r going to verify this through ur testbench
2) go through the synthesis log that you are not messed up with those.

hope this will helps u

ipsips said:

3. that's more complicated, but you should do it synchronously. if you are asking these "elementary" questions, you should stick to synchronous designs for now and not be starting and stopping clocks, but rather enabling or disabling pulses that you use the clock to sample.

Click to expand...

Synchronous is more complicated for implementation due to the multiple driver issues.
Im trying to put Asynchronous behavioural model which can be simulated.

module pulse_gen (input str_clk, input stp_clk, output clk_out);
wire clk_out;
reg int_clk;

initial
begin
forever #5 int_clk=~int_clk;
end

assign clk_out=(int_clk&str_clk&(!stp_clk));
endmodule


Adding TB portion for clarity:

`timescale 1 ns/ 1ns
`include "pulse_gen.v"

module tb
reg str_clk, stp_clk;
wire clk_out;

initial
begin
str_clk=1'b0;
stp_clk=1'b0;
#100 str_clk=1'b1;
#250 stp_clk=1'b1;
#200 stp_clk=1'b0;
#100 stp_clk=1'b0;
#20 stp_clk=1'b0;
#100 str_clk=1'b0;
end

pulse_gen u_pulse (.str_clk(str_clk), .stp_clk(stp_clk), .clk_out(clkout));

initial
begin
$dumpfile("Snapshot.vcd");
$dumpvars(0,tb);
#1000 $finish;
end

endmodule

paulki said:

Synchronous is more complicated for implementation due to the multiple driver issues.
Im trying to put Asynchronous behavioural model which can be simulated.

module pulse_gen (input str_clk, input stp_clk, output clk_out);
wire clk_out;
reg int_clk;

initial
begin
forever #5 int_clk=~int_clk;
end

assign clk_out=(int_clk&str_clk&(!stp_clk));
endmodule

Click to expand...

That's not a good way to generate a clock.
The issue is, depending on the arrival time of stp_clk and str_clk to the AND gate, clk_out may have longer or shorter pulse width across the different chips with different process corners.
And furthermore, if stp_clk or str_clk have to go through combinational logic, it may cause glitches. Having a glitch on clock net will kill the application.

The better way is, like i said, using a low through latch.

latch (.D(str_clk& !stp_clk). .CKN(clk), .Q(out));
AND (.A(out), .B(clk), .Z(clk_out));

Hi lostinxlation,
Thanks a lot for your inputs. Thats the betterway to implement.... I was just trying to implement the Behavioral model which is no way with good coding style. You've provided awesome answer for the asynchronous glitch issues for the stp_clk and str_clk inputs.
This is what I was expecting from the forum members!!!

-paulki