does NPN bjt integratable with EEPROM process?

hi guys, the beta value for PNP lateral bjt is 3 for typical. if i want to make very accurate bandgap reference, this is far too small.

vertical NPN bjt made out of N+ bury layer is much better, and is better for BGR.

An accurate BGR needs to trim very accurately, so i need EEPROM option to store the trim bits.

however, for MPW runs available (SMIC, for instance), the process options providing NPN bjt and EEPROM are different, for instance, smic18mix and smic18ee.

my question is, is it possible to do so using another process or modify the current mixed signal process?

Possible, yes; they are unrelated features. Whether your
foundry uses (say) poly emitter that is also gate poly of
a sort incompatible with EEPROM, who knows? In any case
you get what's on the menu unless you hire your own chef.
Can you change a process? Sure. Can you afford it? Go
ahead and ask. It'll be fun.

You might ask what other trim schemes are supported at
that foundry in the BJT flow. Like fuse, zener-zap or
gate-zap. Some can be done via a serial line, some not.

You do not need a buried layer for the low currents a
bandgap should run. Vertical BJT is good. Some are better
than others, for low frequency low current (many super
high frequency NPNs are optimized for high injection
and have a very peaky hFE-vs-Ic curve; the beta that
counts, is the beta at the current densities you want to
run).