[SOLVED] LEC Conformal between DFT & PAR

HI!
Thanks to previous help from you. But I still have some question about this verification tool.

I've finished RTL -> Synthesis -> DFT comparison by LEC Confromal verification and it shows correct. Now I face the problem when I tried to do comparison between DFT and Place-and-Route result.

The first one is mismapped question due to additional top module which contains IO pad and my MIPS DFT result. This causes unmapped error and corresponding wrong comparison. For this problem, I've survey the official tutorial and fix it by renaming rule.

The second one is that there is no unmapped key points now but it shows non-equivalence for comparison. I've viewed some schematic and found that there are a lof to do with test_se and test_si which are inserted pins during DFT. I tried to set constraints 0 for these signals to see whether this influence the result. However, it indeed works.

After I did the above setting, I still found that there are non-equivalences. But it turns out to be obvious...they are test_so. These pinout cause comparison failed. They can be fixed by ignored.


Question:
1. I'd like to ask you how do you think about this phenomenon ? Why the test signal will affect the result between DFT and PAR ? As my thought, there is no difference for test signals between DFT and PAR process. All these constraints should applied to synthesis to DFT but not DFT to PAR. I don't know why~

2. When you have non-equivalences problems, how do you fix them ? by renaming first to map correct first ? And then ? I don't know how to do if I found there is non-equivalence if I've fixed all the unmapped key points.

Thanks !
PoLo.

1. I assume that you are comparing the netlist before P&R(after DFT insertion) and post-layout netlist. The backend people want to reorder the flops in the scan chains to avoid the routing congestion and it ends up with formal verif failure since pre and post-layout netlists have different logic within scan chains. By disabling the scan shifting path by test_se=0, reordered scan chains won't be compared and it will pass the formal verif.

2. In general, full mapping should solve all the issue if you have all the pin constraint in place.

Hi,
For "The first one is mismapped question due to additional top module which contains IO pad and my MIPS DFT result".
I think you need instant all the IO PAD in your RTL code manually, then you won't have mismapped problem.

OK. Thanks for both you help. I have never known that the scan chain will be modified during PAR process and this error teach me a lesson.

By the way, do you insert IO pads in the RTL stage instead of PAR stage ?

YuLongHuang said:

OK. Thanks for both you help. I have never known that the scan chain will be modified during PAR process and this error teach me a lesson.

By the way, do you insert IO pads in the RTL stage instead of PAR stage ?

Click to expand...

Of cause in the RTL stage? How can the P&R tool know your IO stander(TTL, LVCMOS, STTL, ...) and the drive strength.
Thanks.