[SOLVED] How to generate a clock signal with Spartan 6?

I'm a noob in FPGA world.
I recently bought a Spartan 6 dev kit (Atlys) from Digilent.
I have read the user guide for clock management(CMT) and found that it has 4 CMT's and each CMT further has 2 DCM's and 1 PLL.
The Atlys has a 100Mhz oscillator that clocks the Spartan.
I want to generate a 54MHZ clock and bring it out on 1 of the I/O pins of bank 2.
Any idea how to start with this?

Ken

Good......
You Start with reading how to use a DCM ref Spartan Ref manual and some app notes.
You can enable and configure these premitives using Xilinx CoreGenerator tool.. While configuring you can check out the DCM datasheet how it is useful.
Check this link it is for Spartan3:**broken link removed**
And this for Spartan6 :http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

amitjagtap said:

Good......
You can enable and configure these premitives using Xilinx CoreGenerator tool.. While configuring you can check out the DCM datasheet how it is useful.

Click to expand...

Thank you for the links and tips. I saw the design templates in Xilinx ISE wasn't aware of the Core Generator tool. Is this also present in the ISE?

---------- Post added at 14:48 ---------- Previous post was at 14:24 ----------

Okay so I found the CoreGererator, its under the Tools ---> CoreGenerator.
Now when I run CoreGenerator, I find IP Catalog ---> FPGA Features and Design ---> Clocking ---> Clocking Wizard

Do I have to use this? Am I on the right track?

---------- Post added at 15:27 ---------- Previous post was at 14:48 ----------

OK, I got the Core Generator to work and got it to output some code.
It used the PLL_BASE primitive and the output is CLK_OUT1, its also used some buffers BUFG
How do I test this now, I need to output this frequency on a I/O pin. Any Idea out to do that?

You can drive the IO pin directly, but it's better practice to use a ODDR with D1 = '1', D2 = '0'. This is important for IO busses -- all of the data can be placed in IO registers. If the clock drives a pin directly, the delay is different. If the clock drives an IO register as above, then the output clock has the same delay as the output data.

permute said:

You can drive the IO pin directly, but it's better practice to use a ODDR with D1 = '1', D2 = '0'. This is important for IO busses -- all of the data can be placed in IO registers. If the clock drives a pin directly, the delay is different. If the clock drives an IO register as above, then the output clock has the same delay as the output data.

Click to expand...

I'm sorry, I couldn't understand what you mean to say, that said I checked the Spartan 6 HDL library and found ODDR2 primitive. Actually I'm using this clock to drive a cam module so
1. Do I need the ODDR2 primitive in the clock path?
2. The ODDR2 has 2 clocks, Set, Reset and Chip enable in addition to D0 and D1 what do I do to those pins?
3. How do I assign the output Q to a I/O pin of bank2.

Rgds,
Ken

As mentioned, the ODDR/ODDR2 is used to reduce clock-data skew. If you only have a clock then it's not a big deal.

The IO registers all have nearly equal clk-out times. Thus, it's just good practice to regenerated the clock in an IO register (ODDR in this case). the other pins are self explanitory -- set = 0, rst = 0, ce =1, clk_b = not clk (need a separate signal)

from there, you just connect the Q output to a signal that drives a top-level port and assign that in the UCF.

permute said:

from there, you just connect the Q output to a signal that drives a top-level port and assign that in the UCF.

Click to expand...

And how to drive a top-level port and assign it in the UCF. I'm sorry Verilog syntax is bit new to me, I will try and figure out the UCF part but if you can just get me on my way with the assigning of Q part.

hey good...
Once you generated required IP. you can instantiate it i your HDL code as an component.
Then you can output Clkout signal on CLK I/Os of spartan6.
is it sufficient for you? or need some more details......Dont worry its very easy now.

amitjagtap said:

hey good...
Once you generated required IP. you can instantiate it i your HDL code as an component.
Then you can output Clkout signal on CLK I/Os of spartan6.
is it sufficient for you? or need some more details......Dont worry its very easy now.

Click to expand...

Thanks for the encouragement.
I'm still stuck up at a point. I have instantiated the IP in a top level module. I have posted another thread for that problem. Many thanks.