Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

hspice convergence error in Ac sweep

Status
Not open for further replies.
M

m555

Newbie level 4
Joined
Jul 21, 2009
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,316
i try to design one rail to rail MOS op-amp
i use orcad for plot the circuit and then by R&H convert to hspice model my AC design have no out put and in .sp file of hspice i see

**diagnostic** dc convergence failure,
resetting dcon option to 1 and retrying

**diagnostic** dc convergence successful
you can increase the efficiency of the
operating point calculation by setting dcon= 1
in the .option statement
is my problem for this massage ?
 

What is R&H?

Your error message suggests that the simulation results did converge which would suggest that isn't the problem. However, the fact that the simulation is struggling to converge could mean you have a floating node and hence a drawing mistake or circuit design error.

Keith
 
  • Like
Reactions: m555

    M

    m555

    Points: 2
    Helpful Answer Positive Rating
sorry I mean P&H that transfer orcad file to HSPICE file
thank for your solution but there is not any float node in my design
 

It would be useful if you posted the circuit and netlist.

Keith.
 
  • Like
Reactions: m555

    M

    m555

    Points: 2
    Helpful Answer Positive Rating
I copy whole my .sp file here

[MOD - removed Spice data]
 

Could you post it as a zip attachment? Also, a schematic.

Keith.
 
  • Like
Reactions: m555

    M

    m555

    Points: 2
    Helpful Answer Positive Rating
This is whole file of my design
 

Attachments

  • op.zip
    27.6 KB · Views: 83

It would be useful to have a circuit but I have stripped out the superfluous bits in the list file and removed the sfvtflag = 0 from the models (my simulator doesn't seem to like that) and it simulates OK. VOUT is a gain of 50dB with a UGB of 171MHz. Is that what you were expecting?

Keith.
 

How did you simulate it?
This output is not really what i need.I need gain of 80dB and UGB of 200M
but if my design reach to this result is really good for me and i can improve my result .My more important problem is that i cannot see any out put for my design.
 

I use SIMetrix. I simply used you list file and stripped out the superfluous stuff so I was left with the models, netlist & AC command. What do you get when you simulate? Zero gain? It would seem strange that running the same netlist on two simulators produces different results. Are you sure you are probing the output correctly? I probed VOUT.

Keith
 

I get nothing when simulate.
 

What do you mean by "nothing"? Have you looked at various nodes within the circuit? Have you looked at the DC operating point? You still haven't posted a circuit diagram.

It is clear that the netlist is OK - I got some sensible results from it. So, that would suggest there is something wrong with how you are probing the circuit to view the results.

Keith.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top