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Interview Question Qualcomm,PMC Sierra

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withloveshyam

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I was asked "How to verify a 16 bit adder and a 256 bit counter."

I was asked how I will develop a test plan to effectively test the above circuits. They dont want the exhaustive testing of the circuit.

Please share your answers.

Many Thanks!
 

Formal verification is the simplest and quickest way to verify arithemetic operation nowadays. Do they not like this answer ?
 

Do you mean assertion and coverage checking?
Ya I told them that, But they want me to give some test vectors and check, which will provide maximum coverage i guess.
They asked me to develop a test plan to test the circuitry.
In that case can you help me with the test vectors that will provide maximum coverage...
 

you can do constrained random coverage driven test environment
 

They want me to provide some test vectors that will provide max. coverage i guess. They dint accept this answer when i told them.
 

Different test vectors can be created using variables required as random and than post randomize the thing. The different number of transaction can be give in the test cases
 

First, create a test that exhaustively checks the 16 bit adder. Since the 16bit adder increments, you only need 64k cycles to verify it. Second, create a test that passes carry from lower 16bits to upper 16bits.
So, one test vector for 16bit adder verifications, and a few more for the whole 256 bit incrementor.
 
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