Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I think you missed the whole point of the presentations...
The point is to share knowledge & teach people different aspects of VHDL, We haven't recommended any usage of any package over the other...
The point is how to search for functions & operators in different packages & try to use what is useful for your design...this applies to numeric_std , std_logic_* , math_real packages or whatever packages you have access to
The examples try to use those packages that are most commonly used "std_logic_*", however it doesn't recommend the usage of any to follow good coding practices
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
