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Architecture for 1.2V 50MHz GB op amp

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ashik_na

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Dear all,
I want to design a low voltage op amp for interfacing with ADC ( at input stage ) .Supply is 1.2 V and it requires a 50MHz gain band with. ( almost flat upto 50MHz ).
Any one please suggest me , which architecture can be used here ? please reply with circuit. Has PMOS diff. pair more advantages than NMOS ?
 

Re: 1.2V 50MHz GB Op amp

Well it sounds like since you have a supply of 1.2 you must be in 0.18um or 90nm cmos. Is this correct? Also when you say 50MHz are you talking 3dB bandwidth or Gain bandwidth product GBW ( unity gain BW)? Also what type of DC open loop gain do you need. If it is not important I would say in these technologies and with a GBW only 50MHz you could get away with a single stage or two stage due to it being slow. once again I need to know your open loop DC min. As for NMos or pmos inputs, PMOS inputs have lower 1/f noise and you can put them in there own well to reduce the body effect on your threshold. It really depends also what your input CMR is?
Hope this helps
Jgk
 

Re: 1.2V 50MHz GB Op amp

Thank You for your consideration.
My aim is , to design an op amp acting as a buffer to drive the CDAC capacitor of high speed sampling SAR ADC ( order of 200 Msps ).

1.we are using 65nm tehnology with 1.2V supply.
2. 3db bandwidth should be > 50MHz
3. Should have high slew rate.
4. open loop gain - almost >55db.

please suggest me an op amp circuit , which compromise the above concerns .
Thanks again.
 

Re: 1.2V 50MHz GB Op amp

Unity Gain Bandwidth=fT=(A0)*(f3dB)=[10^(55/20)]*50 MHz ≈ 28GHz ... !!!

I would suggest that you must first understand & clarify your specs and then decide the circuit that will implement your op amp...
 

Re: 1.2V 50MHz GB Op amp

How much gain do you need? 20dB? 40dB?
GBW=gain*band, which is the most critical spec for Opamp design. If it is used in continuous-time amplifier or filter, you could use some tricks to achieve the high bandwidth. But, it's for ADC, you may have to consume significant power for it. A traditional second-stage amplifier seems fine to me.
 

ashil_na, I think the 50MHz 3db bandwith is a spec when the opamp is in closed loop configration. Otherwise, things would be really hard just as jimito13 suggested, even in 65nm process.

If so, many structures of opamp could be your candidates. As the opamp is for a buffer, a two stage struture with relative high output voltage would be better. Still it is up to your application scenario.
 

Also don't forget if this is a follower and your DAC is going to have a large input voltage range, which would be a good thing, better DR!! You will need a rail to rail input! amplifier!
Jgk
 

jgk2004 said:
if ... your DAC is going to have a large input voltage range, ...
Click to expand...
DACs always tend to have r2r input voltages. At all bits, I bet! ;-)
SCNR, john!
 

Also how many bits resolution will your SAR have? This will set your open loop gain (Ao) by its closed loop error. Input((Ao/(Ao+1))=output. This will most probably determine how many stages your amplifier needs along with GBW, which if your sampling at 200MHz I would think you would need alot greater then 50MHz..... I am no SAR designer but I would say(guessing) atleast 2 to 3X Fs to hit your settling times.......Any SAR guys have a better estimate?
Jgk
 

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