DC resistance of a via

Hi all,

I was wondering if it is possible to extract the ac and dc resistance value of a via using HFSS and if so how?

I tried playing around with HFSS and all that its simulation was able to provide me was S,Y,H,Z, parameters etc.

please help =)

Thanks in advance!

That kind of tool is only as good as its inputs. You would
be better off in the real world, I think. Especially as a lot
of the time, vias don't turn out looking as pretty as drawn.
Bet too, on using beds of them instead of singles, and
proximity / fringing effects galore.

If I was serious about this I would be putting S-param
pad cages around geometry-series and measuring the
real deal. Otherwise you're either working on fiction, or
waiting for someone else to have done that very thing
and boil the data for you.

People use to calculate DC resistance from cross-section and length of a conductor. As far as I'm aware of, it works with vias, too. The most unsure point is the exact copper thickness, which can be actually varying between PCB manufacturers and batches for a given via geometry. AC resistance of the via would refer to series inductance only and can be fairly estimated by magnetostatic analysis tools. The more challenging point is to determine the transmission line parameters of vias, which can be only reasonable related to the embedding trace impedances and requires knowledge of the PCB layer stack setup and design rules, e.g. via antipad clearance. Of course, recent electromagnetic simulation tools can perform the analysis for you, with correct input, as already mentioned. I don't think, that it's rather helpful to calculate S parameters of individual vias. You would rather calculate transmission lines with vias treated as discontinuity.

I've had the pleasure of looking at a whole lot of SEM photos
and vias in aluminum systems are very rarely a solid fill, with
the sidewall thickness very variable. I've seen processes that
ran consistently below 40% step coverage. Others that run
"mostly" 100% but have rogue vias that void out almost
entirely when they are in large beds. Trust nothing. I guess,
is my point.

A tungsten plug via in a planarized process would be more
uniform (though you could expect large variation in cross
section, whatever your lithography spec is for via tolerance
as a minimum) and similarly in L for ILD thickness control.

Beds of close spaced vias ought to be an interesting solver
problem, L will go as something well less than 1/N I am sure.
Just like two bond wires to the same post, don't halve L.

I see, that I missed the IC design category. Caclculating via R and L from the 3D geometry would be possible as well. But i fear, all nominal geometric data, for metal layer as well as vias won't be more than an estimation in IC manufacturing.

Our foundry's PDK stated a typ. via DC resistance of 5Ω, a max. (ss process) of 10Ω per via for every via of a 5M .18µm process, allegedly valid for 3σ or 99.7% of a Gauss distribution.

Double vias weren't enforced then (2004). However double contacts.

Hi Guys,
To extract the via's resistance, just use Ansoft Q3D, or Apache PaksiE, such tools employs FEM solver to extract physical parasitic parameter of interconnects from DC to AC. By using HFSS, just convert S/Z/Y matrix to equivalent RLCK using T-model or PI model. But this only valid for narrow band spice model.