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sysgen design : multiple clock domains

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pratheek

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how to specify multiple clock domains in xilinx sysgen
i want my modules to be clocked by two external clock signal
ie, my uart should run at 16MHZ clock , and my image processor sending the sync out throuh uart for debugging work at 80MHZ
 

Hi,

Depending on the FPGA you are using in your design, it sounds like you need to implement a DCM driven by a single external clock. Here's a . I have also uploaded a very useful Xilinx tutorial on how to implement the DCM in ISE. In short the DCM can synthesize various clock frequencies, phases, delays, etc. The various clock signals can drive particular segments of your design. Let me know if you need any further guidance.

Good Luck with your project!
 

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Well, there are always limits. These depend on frequency of the clock input, multiples of and the actual Spartan 3E model your implementing your design. I have attached an application note from Xilinx which details those limits as well as other specs.

Hope this app note helps!
 

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Are you sure you need 2 external clocks?

Since 80 / 5 =16, maybe you could use just the 80 MHz external clock, feed it to a DCM and divide by 5 to derive the 16 MHz clock for your uart. (Also, see the appnote above, in bigdogguru's post). By using a DCM you can at least be sure of the phase relationships of the 2 clocks. This would not be the case if you were using 2 free running clocks.

hope that helps!
 

actually my uart design calls for external clock to be given seperately from the board, even though 80/5 == 16 MHZ seems an obvious option i want two separate clock domains.
 

you might need to write some VHDL or find some way to instantiate something like a fifo.
 

i want to know how to design with multiple clock domains through sysgen.

both clocks are external to fpga
 

pratheek said:
i want to know how to design with multiple clock domains through sysgen.

both clocks are external to fpga
Click to expand...

Sounds like you might want to use a fifo for that, as permute suggested.
 

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