Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The critical path analysis indicates with clock element to clock element path contains the longest (in timing point of view) path.
That indicates the maximum speed of the design.
The path could be from input to clock element or clock element to output or input to output.
By clock element, I mean flip-flop, clocked memories..
The false path analysis, I beleive (because I don't call like this), it's to check the SDC doesn't provide unwanted false path. When a path is declare as false path, the timing engine does not take account this path, and then does not check if this one could be the critical or not.
The false path is provide by the SDC to synthesis tool and P&R & STA.
The critical path is analyse along the flow, synthesis-P&R-STA.
Critical path is the path in the circuit that has maximum timing violation or that has maximum delay. So the frequency of the circuit is dierctly dependant on the critical path and hence its analysis.
False paths are those paths which may be physically present, but logically, it may be an invalid path. For eg if there are two Muxes connected serialy with a common select line, the path from A pin of mux 1 to B pin of Mux 2 is invalid and hence need not be taken into consideration for timing analysis
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
