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[SOLVED] modelsim---the testbench for user define primitive

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fareen

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how to write a testbench for udp02467???
i wrote a program whose compiling is just fine but its giving error when simulating
program is given below
// test bench for UDP 02467
module assi;
reg A,B,C;
wire x;
user_define_primitive udp(A,B,C,x);
initial
begin
A=1'b0;B=1'b0;C=1'b0;
#100
A=1'b0;B=1'b0;C=1'b1;
#100
A=1'b0;B=1'b1;C=1'b0;
#100
A=1'b0;B=1'b1;C=1'b1;
#100
A=1'b1;B=1'b0;C=1'b0;
#100
A=1'b1;B=1'b0;C=1'b1;
#100
A=1'b1;B=1'b1;C=1'b0;
#100
A=1'b1;B=1'b1;C=1'b1;
#100 $finish;
end
endmodule
//User defined primitive
primitive crctp (x,A,B,C);
output x;
input A,B,C;
//Truth table for x(A,B,C) = sum of (0,2,4,6,7)
table
// A B C : x
0 0 0 : 1;
0 0 1 : 0;
0 1 0 : 1;
0 1 1 : 0;
1 0 0 : 1;
1 0 1 : 0;
1 1 0 : 1;
1 1 1 : 1;
endtable
endprimitive
module declare_crctp;
reg x,y,z;
wire w;
crctp(w,x,y,z);
endmodule






the error its giving
Loading work.assi
# ** Error: (vsim-3033) D:/New Folder (2)/udp.v(5): Instantiation of 'user_define_primitive' failed. The design unit was not found.
# Region: /assi
# Searched libraries:
# work
# Error loading design
plz sumone help me
its urgent
assignment due today
 

yes
the compiling is fine,
only problem is coming in simuilation
 

yes
the compiling is fine,
only problem is coming in simuilation

Go by this process:
1) Copy your code in a text file.
2)close modelsim.
3)Open a working program by double clicking its source file that you have saved in its directory.
4)copy the code from that text file where you saved.
5)Then overwrite the code over the running code by deleting it.
6)save the code by save as using different name &then compile & simmulate.
 

how to write a testbench for udp02467???
i wrote a program whose compiling is just fine but its giving error when simulating
program is given below
// test bench for UDP 02467
module assi;
reg A,B,C;
wire x;
user_define_primitive udp(A,B,C,x);
initial
begin
A=1'b0;B=1'b0;C=1'b0;
#100
A=1'b0;B=1'b0;C=1'b1;
#100
A=1'b0;B=1'b1;C=1'b0;
#100
A=1'b0;B=1'b1;C=1'b1;
#100
A=1'b1;B=1'b0;C=1'b0;
#100
A=1'b1;B=1'b0;C=1'b1;
#100
A=1'b1;B=1'b1;C=1'b0;
#100
A=1'b1;B=1'b1;C=1'b1;
#100 $finish;
end
endmodule
//User defined primitive
primitive crctp (x,A,B,C);
output x;
input A,B,C;
//Truth table for x(A,B,C) = sum of (0,2,4,6,7)
table
// A B C : x
0 0 0 : 1;
0 0 1 : 0;
0 1 0 : 1;
0 1 1 : 0;
1 0 0 : 1;
1 0 1 : 0;
1 1 0 : 1;
1 1 1 : 1;
endtable
endprimitive
module declare_crctp;
reg x,y,z;
wire w;
crctp(w,x,y,z);
endmodule






the error its giving
Loading work.assi
# ** Error: (vsim-3033) D:/New Folder (2)/udp.v(5): Instantiation of 'user_define_primitive' failed. The design unit was not found.
# Region: /assi
# Searched libraries:
# work
# Error loading design
plz sumone help me
its urgent
assignment due today

Please note this line:
user_define_primitive udp(A,B,C,x);
and line
primitive crctp (x,A,B,C);

Maybe, you need change to:
crctp udp(A,B,C,x);

Try it.
 

yx.yang
i tried what u said but its giving the same error.
sam,i have tried ur method also but no sucess:(
 

yx.yang
i tried what u said but its giving the same error.
sam,i have tried ur method also but no sucess:(

This must be work.

module assi;
reg A,B,C;
wire x;
crctp udp(x,A,B,C);
initial
begin
A=1'b0;B=1'b0;C=1'b0;
#100
A=1'b0;B=1'b0;C=1'b1;
#100
A=1'b0;
....
 

yx.yang
thank you!!!!
done with my assignment
thanks a lot once again
:)
 

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