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why are both pull-up and pull-down devices are NMOS

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euchee

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Hi, Experts:

I am looking at one IO buffer design from other Sr person, he used all N devices for both pull up and pull down, please refer to the schematic of attachment.

Everyone says N pull up will reduce swing from VCC to VCC-vth, can anyone explain why he designed this?

Thanks a lot.
 

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NMOS have a much higher conductance per layout area.
Discrete NMOSFETs are much cheaper per Ron*BV than
discrete PMOSFETs, same reason. So you see NMOS-NMOS
totem poles all the time in power switching. These usually
have a bootstrapped gate drive (high side source referred)
which eliminates the VT-drop problem. The problem may be
in your assumptions about gate drive levels, which are not
shown.
 
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