Inverter: Design Question - very interesting

Hi All,

I am using this book: Basic CMOS Cell Design by Etienne Sicard.

I'm trying to simulate everything for better understanding.

At page 96, Section 4.3 there is an introduction to the "Inverter Layout".

My question is about this:

p-channel MOS switches half the current of the n-channel MOS.

I understand the reason:

let's say Width and Large are the same for both nmos and pmos, then we have:

Ids(nmos) is proportional to the mobility of the electrons (Uo=0.068 without units)

Ids(pmos) is proportional to the mobility of the holes (Un=0.025 without units)

which is to say Ids(nmos) is aprox. 2.72 times Ids(pmos).

that's the reason why they recommend to use Wpmos=2*Wnmos, to compensate.


Now, I am trying to simulate this to see a difference in the current values (Ion), but that's not the case.

Attached you will find:

1. spice netlist

2. screenshot of the schematic

3. screenshot of the simulation results

4. the text that I'm using for study.


So, I was expecting that if Id(M1) (nMOS device)saturates at about 10uA, then Id(M2) (pMOS device) should saturate at about 5uA.

As you can see in my model definition I set the mobility for the pmos and the nmos.

But the results are almost the same.



Thank you for your time and any suggestion.

Best Regards,

here the spice netlist:


V1 gate_nmos 0 2
V2 supply 0 5
M1 supply gate_nmos 0 0 my_nmos l=1u w=1u
V3 supply gate_pmos 2
M2 0 gate_pmos supply supply my_pmos l=1u w=1u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~1\LTC\LTSPIC~1\lib\cmp\standard.mos
.model my_nmos nmos (kp=20u Vto=+1V uo=0.068 )
.model my_pmos pmos (kp=20u Vto=-1V uo=0.025 )
.dc v2 0 {Vdd}
.param Vdd=5.0
.backanno
.end


below the images:

I am a bit rusty at this, but hopefully someone will jump in with some proper device physics, but I think it is the KP that has a marked effect on the saturation current. KP should be around 24u for NMOS and 8u for PMOS depending on the process. I don't think u0 comes into the equation.

Keith.

---------- Post added at 20:00 ---------- Previous post was at 19:49 ----------

Also, I think a value for gamma would make sense - around 0.8 for NMOS and 0.4 for PMOS.

Keith.

KP=u0*Cox; however some models if you specify KP will not
bother with the u0 based calculation. Or so I recall, back
when I used / made LEVEL= models instead of using other
peoples' BSIM.

Hi again Keith,

thanks for your suggestions and time.

Well, Friday night, and since one hour I was checking what the problem could be (30 minutes more documenting the results here).

I read your hint about Kp and Gamma. That made me pay more attention to the parameters and I found the attached table (see attached table).

As we can see in this table:

GAMMA: Bulk threshold parameter = 632455 (for both pmos and nmos)
KAPPA: Saturation field factor = 0.01 V–1 (for both pmos and nmos)

that means for the PMOS and NMOS Gamma and Kappa are the same.

I hope you could read the last attachment where they explain that if Wn=Wp and Ln=Lp then the Ids Current for the NMOS is proportional to the mobility of the electrons and the Ids Current for the PMOS is proportional to the mobility of the holes, so:


Ids(nMOS) ~ Mn and Mn=0.068

Ids(pMOS) ~ Mp and Mp=0.025

this parameter is called in spice Carrier mobility, and is represented by Uo.

for that reason:

Ids(nMOS)/Ids(pMOS) ~ Mn/Mp = .068/0.025 = 2.72

which means that Ids(nMOS) is aprox. 2.72 times bigger Ids(pMOS)

that's why they do recommend to make Wp aprox. twice Wn (actually almost 3 times, 2.7), to compensate this current difference and to compensate switching discrepancies (switching from 0 to 1 should take approximately the same time as switching from 1 to 0).


So far so good, the problem was that the simulation was not showing the expected difference in the currents.

I just made a change in the models and now they look like this:

.model my_nmos nmos (level=3 uo=0.068 )
.model my_pmos pmos ( level=3 uo=0.025)

and now the simulation works fine.

attached you can see the screenshots. the schematic is the same, I only changed the model definition.

if I use Wn=Wp=1u and Ln=Lp=1u I can see that the Ids(nMOS)=4.7nA and Ids(pMOS)=1.73nA.

To compensate I am going to use Wp=2.72u, Wn=1u, Ln=Lp=1u and I get Ids(nMOS)=Ids(pMOS)=4.7nA

The demonstration is done: the difference is due to the different Carrier mobility parameter uo.

Thank you very much for your suggestions, they helped me to get to the solution of the problem.

Have a nice weekend!







---------- Post added at 22:21 ---------- Previous post was at 22:10 ----------

Thanks also to dick_freebird. Yes, indeed, then Kp is proportional to uo.

For my simulation it is enough if I define the model like this:

.model my_nmos nmos (level=3 uo=0.068 )
.model my_pmos pmos ( level=3 uo=0.025)

also as Keith mentioned "KP should be around 24u for NMOS and 8u for PMOS depending on the process" which is actually 24/8= 3 ~ 2.72

Have a nice weekend!

---------- Post added at 22:27 ---------- Previous post was at 22:21 ----------

keith1200rs said:

I am a bit rusty at this, but hopefully someone will jump in with some proper device physics, but I think it is the KP that has a marked effect on the saturation current. KP should be around 24u for NMOS and 8u for PMOS depending on the process. I don't think u0 comes into the equation.

Keith.

---------- Post added at 20:00 ---------- Previous post was at 19:49 ----------

Also, I think a value for gamma would make sense - around 0.8 for NMOS and 0.4 for PMOS.

Keith.

Click to expand...

from the table gamma is the same for nMOS and pMOS and actually:

GAMMA: Bulk threshold parameter = 0.4^0.5 = 0.632455 (for both pmos and nmos)

Exactly, Kp is proportional to the carrier mobility and 24(nmos) / 8(pmos) = 3 ~ 2.72 ( uo(nmos)/uo(pmos)=.068/0.025 = 2.72 )

Thank you!

It sounds like Dick's statement that if you specify Kp it ignores u0 is correct.

I originally tried it with some 'real' models and it worked as expected so I assumed the model was the problem.

Keith

I think the model used for spice simulations (the level) is extremely important be it spice, virtuoso hspice etc. I appreciate the Op's effort in trying out these experiments. But be aware that this may be feasible in very basic building blocks but as the circuits get more complex it may not be a good idea to try and match theoritical results with simulation results.
:thats where the present gm/id method is very helpful.

My guess is tht if you had tried this experiment on virtuoso cadence you wud not have seen the discrepancies in the first place, because it uses an advanced MOS model in its simulator.

If you try it in ANY simulator with a complete model you won't see the problem but that does not make it wrong to try to understand which parts of a model do what. It can be useful knowledge when you need to start editing models.

Keith

i did not want to imply that it is wrong. My apologies if my post indicated that way. i just meant, that i had tried similar things, but with bigger circuits, it may not be feasible to do analysis in this fashion.

keith1200rs said:

It sounds like Dick's statement that if you specify Kp it ignores u0 is correct.

I originally tried it with some 'real' models and it worked as expected so I assumed the model was the problem.

Keith

Click to expand...

Yes, that was exactly the problem I had in the simulation. If I define the models like this:

.model my_nmos nmos (level=3 uo=0.068 )
.model my_pmos pmos ( level=3 uo=0.025)

you can see the uo effects clearly.

But if I declare kp before uo, like this:

.model my_nmos nmos (level=3 kp=20u uo=0.068 )
.model my_pmos pmos ( level=3 kp=20u uo=0.025)

then the parameter uo will be ignored, kp has priority over uo.

I don't know exactly how the simulator makes the calculations.
Probably because kp is proportional to uo then if I declare the kp(nmos)=kp(pmos)=20u then the uos are considered to be the same, or just ignored (because they are implicit in the declaration of kp)

Thanks!

You can probably find out what equations are used from the Berkeley web site but you will have to do a lot of reading and you will end up learning more about simulators and models than transistor characteristics, which I assume is what you wanted to do!

Keith