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Help me! LDO output voltage variation..

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tyeiei

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I designed capless LDO and measured it.
There are two same LDOs.
One output is floated(just connected to pad), and the other is connected ESD NMOS.

Hmm. measured data is different!

I don't know why... Anybody can help me?

w/ ESD IO NMOS w/o ESD IO NMOS
BGR LDO output BGR LDO output
Sample Vref 0 load 100mA Vref 0 load 100mA
Simulation 1.16 1.81 1.80 1.16 1.81 1.80
test#1 1.20 1.88 1.87 1.17 1.81 1.73
test#2 1.19 1.86 1.86 1.15 1.80 1.73


feature :
5V input to 1.8V output.
No external cap (capless)
max. load : 100mA
 

It is peculiar that your vref changes between sides, if
this is a common reference then it suggests an external
measurement / fixturing error.

The right-hand output's load regulation is poor, perhaps
the design has a Kelvin connection to one pad that is
not effective against the other path's I*R drops.
 

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