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Verilog Porgram Implementation

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ashokkumar.am

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Hi Friends,

I'm designing the SMS4 Design in the Xilinx with Verilog Language.

this time i have plan to be implement in FPGA Spartan 3E 250E Kit.

can any one help me how to load the input in rom of (input 128 bits/ key 128 bits).
and also i have to display the result in LCD 2x16 Display.

kindly send me your comments to regarding this issue.

Any thing related to this issue, plz send me. it will very help to us.

Thank you
Ashok Kumar.
 

in verilog, as Xilinx suggests, you can use $readmemb or $readmemh. the ram needs to be a "reg [W-1:0] ram_name [(D<<<1)-1:0];"

you can also use coregen.
 

Does anyone have a workable verilog code for sms4 cipher
 

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