Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Netlist Simulations - Interview question

Status
Not open for further replies.
G

gold_kiss

Full Member level 4
Joined
Sep 11, 2002
Messages
211
Helped
7
Reputation
14
Reaction score
4
Trophy points
1,298
Activity points
1,789
netlist simulations

Hi,
This is a pretty common interview question.

What is netlist simulation? After all why is it so essential part of design cycle?
What do we acheive by doining netlist simulation?

Cheers,
Gold_kiss
 

hi, good_kiss

For my opinion, the netlist simulation is the Gate-level simulation. After synthesis, you can get the netlist and the SDF file(only have the cell delay). Annotate the SDF file into your netlist, then simulate it for your dynamic timing verification.

After you finished the functional verification and synthesis, you must do the STA and netlist simulation for confirming your design. So it is on the critical path of design flow.
 

If this is the Q in any inerview,
be happy you are a very lucky person.
 

i ment for interview .

edit your last post instead of posting a reply if it's only few minutes apart!!!
/davorin
 

AlexWan said:
hi, good_kiss

For my opinion, the netlist simulation is the Gate-level simulation. After synthesis, you can get the netlist and the SDF file(only have the cell delay). Annotate the SDF file into your netlist, then simulate it for your dynamic timing verification.

After you finished the functional verification and synthesis, you must do the STA and netlist simulation for confirming your design. So it is on the critical path of design flow.
Click to expand...


of course you can do simulation after syn, but you have to fix all hold violation, before doing so, which needs extra effort and is not so nice to do this after layout, which will solve the hold violation more easily.

still some designer believe to do the netlist simulation in an early stage will find some design issues, which can not be found by STA tools

regards
 

gerade said:
still some designer believe to do the netlist simulation in an early stage will find some design issues, which can not be found by STA tools
regards
Click to expand...

I think after finishing the functional verification, we can confirm our functional system can operate! So after syn, we should only do netlist simulation(30%), STA(60%) and conformal(10%). I should pay our attention to STA.

and for hold violation, I think we may use the command in the syn tools for reduce that.

good luck!
 

netlist simulation is use to confirm the correctness of your design in term of functional. But gate level netlist simulation normally took longer time to simulate. Beside netlist simulation, engineer will perform formal verification using Formality..
 

yes formal verification is neccessary, still gate level netlist simulation is not only for functional, but also for timing issues, which are not cover by STA. our project already proved this.

AlexWan, TNX for reply. I will look at DC again.
 

from experience we focus on STA, and if we have time we will run all the cases using final netlist with delay back annoted.
 

zyphor said:
from experience we focus on STA, and if we have time we will run all the cases using final netlist with delay back annoted.
Click to expand...

this usual way. and works well. really can find some problem. but due to the runtime. simulation pattern for netlist simulation must be purposeful
 

Post-layout simluation is important in design cycle,
It's operation is same as the real chip.
 

but post-layout simulation is time-consuming, as long as forever.
 

gerade said:
Alexwan and other guys,

how about conformal. powerful? how about its runtime.
Click to expand...

For my opinion, before your synthesis, you must ensure you finished the function verification, 100%. So after syn, you use the Conformal to compare the Gate-level and RTL. This can ensure the function of netlist. Through this way, we spend a few time for finishing the functional verification of Gate-level.

Comparing the process that do pre-simulation for functional verification, it is very fast.
 

it is amazing.

it seems that formal verification is extremely important for UDSM design. it is why now magm@, c@dence and syn0psys are going to have their own formal verification tools.
 

gerade said:
it is amazing.

it seems that formal verification is extremely important for UDSM design.
Click to expand...

ye
With the size of design growing, the designers can't have more time to run pre-simulation/post-simulation for funcational verification. They need more time to care for timing. So the conformal will help the team to accelerate the step.

Gerade, What's the tools of Magma for conformal?
 

Do we still do any gate level simulations??? In our company gate-level simulations was long abandoned. Today all we do is STA and formal verification.
 

Hi

You can find this info by using search box in the top of website with some keywords related before posting questions.

If you want to get more materials that related to this topic, you can visit: Free interview questions

Best regards.
 
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top