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how to use nested always?

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xpratx

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hi,

i was trying a nested always statements.
always @ (posedge var1)
begin
..
..
..
@ (posedge var2)
begin
..
..
..
end
end

now i don't know if this is correct or not but the compiler doesn't step even into the first always block.
can anyone explains how does these nested always work
 

I am still new to the field, but whatever literature that I have come across I have not found anything like this. I tried it in my simulator, it shows error. Moreover I dont see a need to use a nested always block. You can control the flow and assignments using the blocking and non blocking statements.

Also when you are synthesizing it, if somehow you pass the compilation, it wont.
Perhaps you could post what you are trying to achieve with the nested always, other ways to achieve it may be explored.
 

It doesn't make sense that multiple always statements with posedge are nested.
It means that 2 posedge events happen EXACTLY at the same time, which is not realistic in hardware. Verilog is a HDL that describes the hardware and frankly I think something that cannot be realized by actual hardware shouldn't be used even though it's possible. And I don't think there is a need to have such events in the simulation either.

if you want to detect posedge of var2 after the var1 event, use wait statement(not synthesizable. Simulation only).
 
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alway @ (posedge clk)
..
@(posedge clk)
..
@(posedge clk)


this kind of nested always works. so i was trying just for my knowledge.
anyways thanks
 

always cannot be nested in verilog. always staements are processed paralling in hdl

two or more always statement can be used in a program to achieve the function .
 

xpratx said:
alway @ (posedge clk)
..
@(posedge clk)
..
@(posedge clk)


this kind of nested always works. so i was trying just for my knowledge.
anyways thanks
Click to expand...

What you describe above and in the 1st post are not nested always statements. @ is an expression to detect the event by itself and when you use it inside always block, it would be one time event detection for every always loop, so that it works inside always statement.
But nesting always statemets won't work(I think compiler crashes).
 
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lostinxlation said:
What you describe above and in the 1st post are not nested always statements. @ is an expression to detect the event by itself and when you use it inside always block, it would be one time event detection for every always loop, so that it works inside always statement.
But nesting always statemets won't work(I think compiler crashes).
Click to expand...

so you mean that
alway @ (posedge clk)
..<--- a statement 1
@(posedge clk)
..<--- a statement 2
@(posedge clk)


if we consider 1 posedge and 0 negedge
for every 1--- statement 1 excute
for every 101 ---statement 2 execute
 

In case of using the same clocks like your example, i don't know how it would behave.
You can run the simulation on the code below and see how ev0, ev1 and ev2 events get triggered with respect to the clock edges on the waveform viewer.
Code: 
event ev0. ev1, ev2;
always @ (posedge clk) begin
-> ev0 ;
@(posedge clk) -> ev1;
@(posedge clk) -> ev2;
end

Another code you can try to understand this is
Code: 
event ev;
always @ (posedge clk) begin
  @(posedge foo) -> ev ;
end
and toggle foo signal multiple times within a cycle and see how ev gets triggered.
 
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