- 26th November 2010, 18:04 #1

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## CMOS Transistor size ratio

Hi

I apologize if this is´t the right forum for this kind of question but i have been searching the forum and have´t been able to find a suitable answer to my problem .

The problem is that I have to size CMOS transistors accordingly to a specific ratio to (under my understanding) get equal rise and fall time.

The design is a four input pseudo-NMOS-gate with the ratio for the NMOS W/L = (1.8/1.2) and for the PMOS W/L = (3.6/1.2) with the foundery of 0.25um.

I just want to be clear that im not looking for the strait up answer to my problem but instead a push in the right direction..

Hope that you understand my description and that you have time to answer.

Best regards Erikwikt.

- 27th November 2010, 06:32 #2

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## Re: CMOS Transistor size ratio

Hi,

Please go through this PDF for better understanding of sizing the transistor.

http://wwwi.elec.gla.ac.uk/teaching_...gn_4/unit3.pdf

1 members found this post helpful.

- 28th November 2010, 22:30 #3

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## Re: CMOS Transistor size ratio

Hi vlsi123, thanks for the quick answer.

I have been reading the PDF that you linked to me and I think its great! But I have a couple of questions in my way of thinking.

In the problem that i descibled it was said that the ratio for the NMOS (as an example) transistor should be (1.8/1.2).

Because of the fact that it has decimal numbers in both over and under the division sign. Can I simplify it to 3/2? So that I get strait lambdas?

To my second question, I have read from other sources that a rule of thumb is that the with of the PMOS should be twice the with of the NMOS because of the mobility in the material.

Now I am using MicroWind as my design program and from the program I can extract the minimum length of the gate for both the NMOS and the PMOS, which is 2 lambda.

So if the with of the PMOS gate has to be 3 times larger then the length, will the total gate with be [(minimum length) * (the mobility rule) * (the with ratio)] = (2 * 2 * 3) = 12 lambda?

Yours ErikWikt

- 29th November 2010, 11:17 #4

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## Re: CMOS Transistor size ratio

2 members found this post helpful.

- 29th November 2010, 11:17

- 29th November 2010, 16:19 #5

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## Re: CMOS Transistor size ratio

Hi erikl

The size ratio for the NMOS transistor should be 3/2 and 3 (3/1) for the PMOS.

So wont the width for the PMOS be equal to 2 * 3 * 3 = 18 and 2 * (3/2) = 3 (or 6 if i chose the length for the NMOS gate to be 4)?Last edited by erikwikt; 29th November 2010 at 16:53.

- 29th November 2010, 17:29 #6

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## Re: CMOS Transistor size ratio

Again: no, sorry! Why

(minimum length) * (the mobility rule) * (the width ratio) = 2 * 3 * 1.5 = 9

In your equation for the PMOS width, (the width ratio) =__width ratio of__. The mobility ratio of 3 already takes care**NMOS**

NMOS W/L = 1.5 . For similar electrical behavior of PMOS & NMOS use

W/L(PMOS) = (µn/µp) * W/L(NMOS) ≈ 3*W/L(NMOS)

You don't need to double the PMOS ratio (the doubling at your original source PMOS/NMOS W/L ratio is caused by a mobility ratio assumed to be =2); now we calculate with a mobility ratio=3.

So finally: W/L(NMOS) = 3/2 (or 6/4) and W/L(PMOS) = 9/2 (or 18/4)

Hope I could present this graspably!

BTW: If you design for a mobility ratio of 2 or of 3 depends on your personal feeling: quite a lot of books and papers use a ratio of 2 (hence the PMOS is a bit wispier than the NMOS), it is (somewhat) easier to calculate , and - last not least - it saves costly silicon area. A design ratio of 3, however, is closer to reality, better for NMOS/PMOS symmetry (concerning Ids, gm, fan out ...), achieves (somewhat) faster circuitry - just is (somewhat) more expensive.

So choose up to your requirements - or up to your taste!

- 12th December 2010, 18:31 #7

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## Re: CMOS Transistor size ratio

Hi again guys. Sorry for the terrible late answer but my studies has been eating me alive....

I just want to thank you guys for the help with my question! =D

It really was a homework if that wasn't clear and I got total points on it as well!

Thanks again for the help!

- 13th December 2010, 13:05 #8

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## Re: CMOS Transistor size ratio

if you just want to get equal rise and fall time,

you can use a capacitor load and tansient analysis,

find the rise and fall time of Vout,

then adjust the W/L of NMOS and PMOS.

usualy,the mobility ratio µn/µp is not equal for different fab process.

but the design theory is the same as what erikl's said.

- 13th December 2010, 13:05

- 5th October 2012, 09:46 #9

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## Re: CMOS Transistor size ratio

Hello,

In a circuit I have changed PMOS of W from 240nm to W/L=540nm/180nm. I want to know for NMOS how much the W from 240nm has to be changed if the L remains the same i.e.180nm? The circuit is being implemented in Cadence.

- 5th October 2012, 09:46

- 5th October 2012, 13:25 #10

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## Re: CMOS Transistor size ratio

Just keep the old PMOS/NMOS ratio. If you want to consider the µn/µp ratio (which is about 4.7 for 180nm CMOS), you could adjust the PMOS(W/L) / NMOS(W/L) ratio for this factor.

- 6th October 2012, 03:42 #11

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- 6th October 2012, 12:37 #12

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## Re: CMOS Transistor size ratio

As the mobility ratio for 180nm CMOS

__bulk__processes is about 4.7 (s. the image below), the PMOS(W/L) ratio should be this factor greater than the NMOS(W/L) ratio, if you want the same drive strength from both transistors. So if you selected W/L=540nm/180nm for your PMOS, your NMOS needs only a W/L=115nm/180nm. For more info see e.g. the book named at the image below.

- 6th October 2012, 19:08 #13

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- 26th November 2012, 13:08 #14

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## Re: CMOS Transistor size ratio

Please consider that all these ratio considerations are just good approximations but not accurate and don't consider effects of layout, temperature and process variation (ss/ff/sf/fs). If you really want a minimal difference between rise/fall times at all corners (for example when creating clock buffers), then you have to numerically optimize the netlist, preferrably an extracted one post-layout.

- 16th March 2013, 06:03 #15

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## Re: CMOS Transistor size ratio

I am designing a 3 input nand gate on microwind( layout level) and on Dsch2-7 (transistor level).

i am given the Nmos sizes: W=4.5 pi L=2.5 pi

with the foundary = CMOS018

I am told to use the same length of PMOS as i used for NMOS. however, i have to find the width of PMOS so that i have equal rise and fall time.

is there a special relationship between width of NMOS and PMOS?? please help out. or direct me to a link.

- 16th March 2013, 10:57 #16

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## Re: CMOS Transistor size ratio

Everything you need is described above in this thread: read it attentively :)

I have a comment, though, on the page you show as an image from David Binkely's book. The values for carrier mobility are strange. Both UMC 0.18u and TSMC 0.18u have a carrier mobilty ratio of approx 2.6, not 4.7 as in Binkley's table.

Slainte!

H

- 16th March 2013, 19:30 #17

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## Re: CMOS Transistor size ratio

Last edited by erikl; 16th March 2013 at 19:35.

- 16th March 2013, 22:21 #18

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## Re: CMOS Transistor size ratio

Since the µ depend on doping, and customers of foundries normally want to use similar designs when going to a smaller technology node, I can scarcely imagine what could bring a foundry to doing this 4.7 ratio ... they'd have to do it on purpose, but for what purpose?

Scottish ... I studied English in Edinburgh, a long time ago :)

- 13th April 2013, 17:47 #19

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## Re: CMOS Transistor size ratio

Sir have you parameters value related to 22nm technology??

and value for voltage suply for this 22nm technology??

thanking you...

- - - Updated - - -

Sir I am not able to download this pdf is there any other pdf like this available??

- - - Updated - - -

value of lambda would be???