Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

verilog hdl program code

Status
Not open for further replies.

hareshcooleng

Member level 1
Joined
Aug 6, 2010
Messages
36
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
ahmedabad
Activity points
1,480
HI all,
dis is d code for simple 4 bit multiplication.
der is no syntax error in dis program.
but the result is not shown.
i mean result is not proper.
so pls correct code nd replay me.
thanx...

module div(sum,B,Q,A,clock,start,e);'
output [4:0] sum;
reg [4:0] sum;
input [4:0] Q,B;
reg [5:0] T;
input [4:0] A;
input clock,start;
reg [10:0] r;
//reg [9:0] S;
input e;
reg z;
reg [4:0] ac,QC;
reg [3:0] sc=4'b0101;

always @ (posedge clock)
begin
if (start)
begin
QC = Q;
ac = A;
z = e;
sc=sc-1;
while (sc!=4'b0000)
begin
if (QC[4])
begin
T=ac+B;
assign {z,ac}=T;
r = {z,ac,QC};
r = r>>1;

sc=sc-1;
$display("count=%b",sc);
end
else
begin
r= {z,ac,QC};
r = r>>1;
sc=sc-1;
$display("count=%b",sc);
end

end
sum={A,Q};
end
end
endmodule
 

sum={A,Q};
sum is an output and A,Q are both inputs.

Other than this, the code listed is probably a poor choice. Its best to avoid "while" in synthesized code -- it more used for testbenchs. "for" is a better choice, but keep in mind that real iterations will cause complexity to grow quickly. For college projects this might be ok, as the FPGA is generally run very slow and is oversized.

sum also uses a blocking assign and is an output. This should be avoided because verilog does not enforce any ordering of always blocks. This means one cycle/sim, the sum will be updated before it is used by an external module. The next cycle/sim the value of sum might be updated after it is used by external modules.

sc is also initialized but doesn't regain the former value at the end of a cycle.

There may be other errors as well.
 

First, is it multiplication ? ur module name says its division !
if it is multiplication, y r u making so complicated ?
keep it simple.... like the one below
for(i=0;i<multiplier;i++){
temp_reg = temp_reg + multiplicand;
}
 

that's not really a good way to do things. Keep in mind that complexity isn't based on the length of the code, but on the synthesized results. A basic way to implement your code is with 15 adders in series (for worst case). This uses a lot of area and has a large propagation delay. some tools won't let you use a non-constant number of iterations as well.

Shift and add is another way to do this, and it has fairly low complexity, with around 4 additions.

But using z <= x*y; is more likely to chose a 256 element ROM (for FPGAs) or whatever the tools are configured for (for ASICs). It makes the code readable, and it works well.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top