sjamil02
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Hi All,
I am designing a push pull shunt regulator circuit for regulation of digital circuit. The block diagram is attached (PushPull_Block_Diagram.jpg). The circuit implementation is also attached (pull_up_schem.jpg --> for pull up function and pull_down_schem.jpg --> for pull down function). The basic idea of this circuit is that the whenever the output voltage go below/higher than the tolerance margin, the output of the pull up or pull down will turn on and source or sink current and hence can maintain the regulation voltage within the tolerance margin. The pull up and pull down circuit is OFF when output is within the tolerance margin. The tolerance margin is set by ( Iset/gm*8 ) where I set is the bias current shown in the schematic and gm is the input diff amp tranconductance and multiplied by the current gain (1:8 mirror ratio).
Few things that I'm not clear on how to simulate this circuit.
(1) How to do transient simulation of this circuit. Since the output is tapped from power supply (1V), if I used ideal dc source (Vdc=1V), then the output voltage will be flat at 1V. Should I put series resistance and how much is the resistance value? Say with peak loading current of 25mA.
(2) How to do stability analysis of this circuit? Should I break the loop at the feedback node and injected test signal? I have tried this and I got negative dB gain.
Thanks in advance for your advice.
SJ
I am designing a push pull shunt regulator circuit for regulation of digital circuit. The block diagram is attached (PushPull_Block_Diagram.jpg). The circuit implementation is also attached (pull_up_schem.jpg --> for pull up function and pull_down_schem.jpg --> for pull down function). The basic idea of this circuit is that the whenever the output voltage go below/higher than the tolerance margin, the output of the pull up or pull down will turn on and source or sink current and hence can maintain the regulation voltage within the tolerance margin. The pull up and pull down circuit is OFF when output is within the tolerance margin. The tolerance margin is set by ( Iset/gm*8 ) where I set is the bias current shown in the schematic and gm is the input diff amp tranconductance and multiplied by the current gain (1:8 mirror ratio).
Few things that I'm not clear on how to simulate this circuit.
(1) How to do transient simulation of this circuit. Since the output is tapped from power supply (1V), if I used ideal dc source (Vdc=1V), then the output voltage will be flat at 1V. Should I put series resistance and how much is the resistance value? Say with peak loading current of 25mA.
(2) How to do stability analysis of this circuit? Should I break the loop at the feedback node and injected test signal? I have tried this and I got negative dB gain.
Thanks in advance for your advice.
SJ
