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Reading verilog port - What is the problem?

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otis

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Reading verilog port with in the same module- What is the problem?

Hi,
I know in VHDL we cannot read the port within the module.

it is possible in Verilog. I used in few places. My colleague says it is wrong. But he does not know why.

I also dont know why.

Could anyone tell what is the problem using/reading output port with the same module in Verilog?

Thanks in advacne
 
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I know in VHDL we cannot read the port within the module.
Click to expand...

What do you mean, if by port you mean the pins of the chip then you can read them if you declare them as buffer output or inout input/output or if you can use an out output and use a signal that stores the last value that was sent to the output and read it from anywhere.

I'm only using VHDL so i don't know anything about verilog

Alex
 
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    otis

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For example,
entity gcd is
port( clk: in std_logic;
rst: in std_logic;
go_i: in std_logic;
x_i: in unsigned(3 downto 0);
y_i: in unsigned(3 downto 0);
d_o: out unsigned(3 downto 0)
);
end gcd;

her the output port "d_o" cannot be read inside the architecture. some thing like "data <= d_o"; you have to do indirectly.

But this is allowed in Verilog. My colleague says it is wrong to use even it is allowed.

That was my question. what is wrong with that.
 

If you write it like this

entity gcd is
port( clk: in std_logic;
rst: in std_logic;
go_i: in std_logic;
x_i: in unsigned(3 downto 0);
y_i: in unsigned(3 downto 0);
d_o: buffer unsigned(3 downto 0)
);
end gcd;

you can read it.
I'm sure it can be done in verilog too but i can't say how.

Alex
 
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    otis

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thanks for the reply.

In verilog it is possible to read the output without any modification.
Again my question is "In Verilog reading ouput diretly is wrong , even though it is allowed. - Why?"

Thanks in advance for your reply.
 

He assigns a value to a port defined as output and then in another part of the code he uses a condition for example which reads the value of that port and does something.
He is asking why is it wrong to read (directly) the value of a port defined as output .

Alex
 
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    otis

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something like this ?

Code: 
module foo (in1, in2, in3, out1, out2);
input in1, in2, in3;
output out1, out2;

assign out1 = in1 & in2;
assign out2 = out1 ? in3 : 0 ;

endmodule
There is nothing wrong with doing this.
 
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    otis

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Nothing wrong..then my colleague seems to be wrong :)

Thanks for your replies!!!
 

I did some research and i found that some people are against declaring a port as buffer and say that you should always declare it as out and use a driver signal which you can read, this is for VHDL
I assume that what your friend told you is the same thing for verilog.

I found some conversations on the topic, mainly VHDL

OUT, INOUT and BUFFER
BUFFER mode ports

Alex
 
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