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can we use two entity in a single vhdl program,

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rourabpaul

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can we use two entity in single program,
and one signal of 1st entity is derived from 2nd entity(I dnt want to use functions)
 

You mean multiple entities in a single source file? Yes.
 

You have two complete entities, including header and architecture body. You instantiate the first as a component in the second entity. Normally, each entity is placed in a separate file, but you also chain both in a single file.
 

Instantiation of a component always implies port mapping.
 

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