problem with fifo buffer and debounced button signals

I need some help implementing a design from the book " FPGA prototyping by VHDL examples - Xilinx Spartan 3 Version". It should be kind of necessary for someone to consult the book in order to help me out.

I've implemented the fifo buffer circuit and the respective test circuit documented in pages 100-104 including also the pushbutton debouncing circuit.

The problem is that the full led lights up immediately after adding data in the buffer having pressed the write pushbutton although the buffer has a size of 4 elements. I cannot write another vector in the buffer unless I push the read pushbutton which in turn lights up the empty led instantly.

It seems as if my buffer has a size of 1 which cannot be the case. I suspect that pressing the write pushbutton produces a long enough signal that takes up multiple clock cycles effectively filling the buffer with the same value. In turn, pressing the read pushbutton has a similar effect reading all data (which are of the same value) emptying the buffer. But then, why the author has added such a counterintuitive example circuit for testing and implementation on an fpga?

Bit confused, glad if someone could help.

What's the clock speed ?
And how do you detect the button pressing ?

Try to make the clock speed extremely slow like 0.5Hz or so if you can.

I'm using the onboard 50MHz clock. I tried to use a slowed time tick but it's not trivial to incorporate it in the design. Using 0.5 Hz I verified that writing this way does not fill the buffer! But then the reading functionality did not work, I guess I broke something in the design.

Button pressing is detected filtered through the debouncing FSM circuit documented in listing 5.6 at page 120 of the book.

To give some more input, I created a testing program counting the debounced vs. bouncing number of button presses using the 7 segment LED. The number of "bouncing" presses is higher (as expected) but interestingly, sometimes one button press counts more presses than one (without any regularity) in both bouncing and debounced counters! Could that be a glitch in my FPGA board?