yans123
Junior Member level 2
Hi,
I created ring oscillator simulation in Cadence Virtuoso .
the ring is made of : INVERTER >>INVERTER >>NAND3>>NOR>>INVERTER
I pull one of the NOR's gate input to gnd , and 2 of the NAND inputs to vdd
so the gates will behave as inverters .
I have some very weird problem with my design , I get the fastest oscillator
when I use minimum width\Length of the transistors. meaning , when I extend the width of the transistors I get slower oscillations .
I thought it may be related to the fact that now the input capacitance
of each gate is bigger so the extra capacitance "wins" the extra current.
but still it is not suppose be kike that .
Does anyone has any idea what might be the problem?
Thanks...
I created ring oscillator simulation in Cadence Virtuoso .
the ring is made of : INVERTER >>INVERTER >>NAND3>>NOR>>INVERTER
I pull one of the NOR's gate input to gnd , and 2 of the NAND inputs to vdd
so the gates will behave as inverters .
I have some very weird problem with my design , I get the fastest oscillator
when I use minimum width\Length of the transistors. meaning , when I extend the width of the transistors I get slower oscillations .
I thought it may be related to the fact that now the input capacitance
of each gate is bigger so the extra capacitance "wins" the extra current.
but still it is not suppose be kike that .
Does anyone has any idea what might be the problem?
Thanks...