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Synopsys synthesis of a full adder cell

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etherios

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I am describing a full adder cell in synopsys and i want to be synthesised with the full adder cell of my 0.13 library but the tool uses the gate implementation. What should i do in order to be synthesised with that cell i want from the library?
 

Re: Synopsys- Synthesis

hi,etherios
If you have the cell of addr, I think you can write the netlist for your addr. Only pay your attention to the interconnection and cell delay.

Good luck!
 

Re: Synopsys- Synthesis

how can we do this in rtl description? Can you be more specific? If you can send me an example
 

Re: Synopsys- Synthesis

you can choose which adder to use, in DC ultra. better read document or the training material for advanced chip synthesis from Synopsys
 

Re: Synopsys- Synthesis

After compile your design using DC ultra, everything will turn into cell. You cannot estimate the types of logic gate that going to used, but DC ultra will give an equavalent function from your trl code.
The type of logic gate after compilation is up to your constraint settings!!
 

Synopsys- Synthesis

use your cell directly. like this:
DW01_add #(35) iad01 ( .A({mo34_01_1[33], mo34_01_1}), .B({mo34_02_1[33], mo34
_02_1}), .CI(1'b0), .SUM(mo35_1_1), .CO(co01) );
 

Re: Synopsys- Synthesis

sorry, I am wrong, you can not specify adder using DC ultra, this one will pick out one itself,

but still before going to compile, during elaboration, you can specify adder in DW. then DC will not choose another one.
 

Re: Synopsys- Synthesis

As regards the reply z81203..

I think etherios means how to force DC to synthesize using 1-bit Full Adder cell from the physical library, not the synthetic laibray (DW01_add is from Synopsys Designware Libray).
The problem is how to force dc to synythesize the code of a process using a 1-bit FAdder cell.

For examble the following SystemC process

void my_process(void) {
sc_logic x,y,z,sum,carry;
x=x_in.read();y=y_in.read();z=z_in.read();
sum=x^y^z;
carry=(x&y)|(y&z)|(x&z);
S_out.write(sum);C_out.write(carry);
}

is synthesized using 2 XOR2 gate cell and an AO22 cell (that contains 2 AND and an OR), although the 1-bit Full-Adder cell of the same phhysical library has smaller area and delay.
 

Re: Synopsys- Synthesis

After so long i have found a solution at least for the structural description of the circuit. If anyone can provide something for the behavioral plz tell me.
Here is the listing

library IEEE;
use IEEE.std_logic_1164.all;
library GTECH;
use gtech.gtech_components.all;

entity adder is
port (a,b,cin :in std_logic;
sum,cout:eek:ut std_logic);
end adder;

architecture of adder is
--synopsys dc_script_begin
--set_map_only {find (reference, "GTECH_ADD_ABC") }
--synopsys dc_script_end

begin
U1 : GTECH_ADD_ABC port map (a,b,cin,sum,cout);
end adder;
 

Synopsys- Synthesis

I think there should be a option in DC or DC ultra to switch off the DW infer。 Is this correct?
 

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