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Starting with VHDL, simple questions

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bazook

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Hi,

i am newbie in VHDL and when i started with designing some questions come to mind:

1. I've found out that using signs '>' or '<' isn't a good practise. What is better way to compare two vectors, especially in 'if' ?

2. What i should avoid if i would like to write in RTL. I know that it shouldn't be sequential so 'process' and 'after' cannot be. Something important else? 'Process' is in RTL undesirable always?
 

where did you learn these things?

> and < are an essential part of the language if you are trying to compare two integers.
And you cannot write any RTL without process.

You can use after, but it will be ignored for synthesis. It can be useful for modelling.
 
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    bazook

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About process i heard probably from someone at my university. It is really good to read that its diffrent. So what is the most important in RTL?
And what about compare two vectors? Should i search other way? I need to use that with counter, out signal is '1' when counter is above chosen value.
 

the comparison thing comes from high speed designs. Especially using counters. assume x increments by 1 per cycle, and the comparison is x > 100, and x resets to 0 at x = 255. I can either have the output be "x > 100", or I can make a register that gets set when x = 100 (asserted on the next cycle), and resets when x = 255.

In the first case, the comparison is "greater than", which has complexity similar to an addition. The second case is "equal", which has complexity similar to an N-input gate. This can be important when the comparison is in the critical path. More modern fabric (V5/V6/S6) reduce the impact of comparisons at high speeds. Small comparisons also have equal complexity as they become implemented using a single LUT (or SLICE).
 
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When i use some kind of counter i usually use std_logic_vector instead of integer and this way (depending on the result you want) you can get away by just checking one bit.
For example when i have a ram address counter which fills at 256k byte the max address value can be 11111111 (8 bit) so instead of checking for this value i use an 8 bit counter plus 1 for overflow (total 9 bits) , then i just have to check if bit 8 of address (the MSB) becomes 1 when address reaches the final value.

000000000 starting address
011111111 final address
100000000 the MSB becomes 1 so stop

this is also useful when you want to divide a clock by 4 (or 8,16...).
To divide by 4 you can use a std_logic_vector(1 downto 0) counter and then use only the MSB (bit 1) as a divided clock

00 bit1=0
01 bit1=0
10 bit1=1
11 bit1=1
00 bit1=0
01 bit1=0
10 bit1=1
11 bit1=1

Alex
 
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alexan_e said:
When i use some kind of counter i usually use std_logic_vector instead of integer and this way (depending on the result you want) you can get away by just checking one bit.
For example when i have a ram address counter which fills at 256k byte the max address value can be 11111111 (8 bit) so instead of checking for this value i use an 8 bit counter plus 1 for overflow (total 9 bits) , then i just have to check if bit 8 of address (the MSB) becomes 1 when address reaches the final value.

000000000 starting address
011111111 final address
100000000 the MSB becomes 1 so stop

this is also useful when you want to divide a clock by 4 (or 8,16...).
To divide by 4 you can use a std_logic_vector(1 downto 0) counter and then use only the MSB (bit 1) as a divided clock

00 bit1=0
01 bit1=0
10 bit1=1
11 bit1=1
00 bit1=0
01 bit1=0
10 bit1=1
11 bit1=1

Alex
Click to expand...

First of all, it would be better to get into the habit of using unsigned for counters. a std_logic_vector is not an integer.

Secondly, using a counter to divide a clock is usually a bad move if you want to drive internal logic. You are likely to get problems with clock skew if you run it at any decent speed.
 

a std_logic_vector is not an integer.
Click to expand...
i didn't say that these are the same, i said that i usually use std_logic_vector instead of integer.

You are probably right about using unsigned instead of integer but my point was that by using a std_logic_vector you can check for a result using less logic (and chip resources).

i usually use small CPLD so i use a counter to divide the clock internally, which way would you suggest to divide the clock?

Alex
 

you are using a std_logic_vector as an integer when you make it a counter. An unsigned is an array of std_logic, exactly like a std_logic_vector, so you can do the same logic with it, but it represents an unsigned integer.
 

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