ICAP Controller Instantiation Problem

Hi all,


I am trying to interact with the ICAP controller on the Virtex5 and I am not really successful so far. The primitive for

the ICAP controller looks as follows:


ICAP_VIRTEX5_I : ICAP_VIRTEX5
generic map (
ICAP_WIDTH => "X32")
port map (
clk => clk,
ce => icap_ce,
write => icap_we,
i => icap_datain,
busy => icap_busy,
o => icap_dataout);


Checking the synthesis report, it shows that one ICAP controller has been instantiated.The next step is to simply write the synchronisation word (0xAA995566) to icap_datain with icap_ce = 0 and icap_we = 0. Normally when receiving the SYNC word icap_out should change to 0xDF, however, in my case icap_out remains at 0x9f which indicates that no SYNC word has been received by the ICAP controller. I tried all different combinations of the synchronisation word, so litte and big endian as well as bit swapping.


Is there anything else I have to consider when trying to interact with the ICAP component. Do I have to specify any constraints in the UCF file. Alternatively, do I need to specify some specific options when generating the bitstream?


Any comments that could solve my problem would be highly appreciated!

Hi Richard,

Have you tried filling the ICAP with some dummy words before sending the SYNC word? I'm not sure about this but I think the controller must have a kind of input buffer. By the way, you need to do bit swapping but at byte level: you swap bits in each byte independently from the rest of bytes (see Virtex 5 Configuration Guide).

Good luck in your efforts, it's not easy to manually drive the ICAP controller.

I guess UG191 & XAPP1100 should help.