Hi,

Im using the XUPV5 Virtex-5 Board with Xilinx ISE 12.1. Within XPS I built up a system design where I instantiated a DDR2 SDRAM memory controller as a user IP-Core, which I created with MIG / core generator before. I connected all relevant ports with my user design and made all neccessary ports external (I also modified the ucf). My problem is, that EDK creates the IO ports (e.g. the data port "ddr2_dq") the the wrapper source file and in the system.vhd as three ports:

ddr2_dq_I : in std_logic_vector(63 downto 0);
ddr2_dq_O : out std_logic_vector(63 downto 0);
ddr2_dq_T : out std_logic;

Of course theese ports dont exist in my memory controller component. The exact type of error is:
ERROR:Xst:2585 - Port <ddr2_dq_I> of instance <ddr2_mem_ctrl_0> does not exist in definition <ddr2_mem_ctrl>. Please compare the definition of block <ddr2_mem_ctrl> to its component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <ddr2_dq_O> of instance <ddr2_mem_ctrl_0> does not exist in definition <ddr2_mem_ctrl>. Please compare the definition of block <ddr2_mem_ctrl> to its component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <ddr2_dq_T> of instance <ddr2_mem_ctrl_0> does not exist in definition <ddr2_mem_ctrl>. Please compare the definition of block <ddr2_mem_ctrl> to its component declaration to detect the mismatch.

what am i doing wrong?

thanks in advance,
sebastian