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Using low voltage process design high voltage block

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xibeizi

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Hi everybody. I am using 18V bipolar process to design a opamp which Power supply can be as high as 36V. How should I design it. Thanks.
 

Can anybody help me?
 

You didn't provide enough info to get help. If this can be done depends on several details:
  • Pure bipolar or BiCMOS process?
  • Which device has to stand the 36V? BJT or MOSFET? Grounded or floating? Which current?
  • If HV-MOSFET, how much voltage would be necessary between G-S resp. G-B?
  • Does the foundry provide a HV option? HV device layout & model available?
  • If not: are you confident to be able to design your own HV device(s) - incl. simulation model(s) - which you may trust?
 
erikl said:
You didn't provide enough info to get help. If this can be done depends on several details:
  • Pure bipolar or BiCMOS process?
  • Which device has to stand the 36V? BJT or MOSFET? Grounded or floating? Which current?
  • If HV-MOSFET, how much voltage would be necessary between G-S resp. G-B?
  • Does the foundry provide a HV option? HV device layout & model available?
  • If not: are you confident to be able to design your own HV device(s) - incl. simulation model(s) - which you may trust?
Click to expand...

I use Bipolar process because My comparator has only 2mv offset, The VCE breakdown voltage of PNP or NPN is 18V,So the input differential pair has only 18V headroom.But the power supply has 2-36V range. If this chip work under 36V, the low commom input voltage may result in the breakdown of the current source PNP, the high commom input voltage mat result in the breakdown of the differential pair, respectively. How can I solve this problem. I design my own HV device? that maybe terrible.
 

xibeizi said:
I use Bipolar process because My comparator has only 2mv offset,
Click to expand...
You can easily achieve a comparator offset < 2mV with standard CMOS processes.

xibeizi said:
The VCE breakdown voltage of PNP or NPN is 18V,So the input differential pair has only 18V headroom.But the power supply has 2-36V range. If this chip work under 36V, the low commom input voltage may result in the breakdown of the current source PNP, the high commom input voltage mat result in the breakdown of the differential pair, respectively. How can I solve this problem. I design my own HV device? that maybe terrible.
Click to expand...

If the ≤36V would just be an input voltage of the chip, this wouldn't be a problem (could be divided down by resistors). If it's actually power supply, however, you definitely need a HV process, or at least a process which - by a special option - allows for integration of HV devices.

Several foundries offer such HV processes/options, s. e.g. these topics.
 
erikl said:
You can easily achieve a comparator offset < 2mV with standard CMOS processes.

As I known, The CMOS process typically have more than 5mV offset. Only bipolor process has less than 2mV offset. Am I right?
Click to expand...
 

Re: Low offset voltage with CMOS process?

erikl said:
You can easily achieve a comparator offset < 2mV with standard CMOS processes.
Click to expand...
xibeizi said:
As I know, The CMOS process typically have more than 5mV offset. Only bipolor process has less than 2mV offset. Am I right?
Click to expand...

No, not at all. Of course - with rather careless layout - you can get > 5mV offset. But if you are ready to spend enough area for big input transistors, and if you care for a highly symmetric, interdigitated and/or common centroid layout, you can definitely achieve an offset voltage ≤ 2mV.
 
You can search for "gate control" techniques for HV design.
But for power control applications, there should be special HV process for design.
Otherwise, using 1.8V process to realize 36V ckts is not easy.

- - - Updated - - -

For EX.
LDMOS in 1.8V process might be a good choice for HV applications.
 

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