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error with TSMC Capacitor pcells

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aarthy_maya

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Dear All,

I m using TSMC 180nm Process. I'm using nmoscap pcell in layout view, when i place two same instances of same size capacitor, i m getting an error " Label short" and saying that PCELL instantiation cell "pmoscap" (unique cell name "pmoscap_PC2") from library "tsmc18rf" has the following property. L=10.84u W=10.84u. There is no error if i place instance of different size.:sad:

please help me on this...
 

Hi,

I had the same problem with my last chip, TSMC 90nm. I had 100+ "Label shorts" when my LVS was run... It does say that schematic and layout match, so I said to myself, that is all LVS is used for and tapedout.... My chip does function completely, so I would say its a cadence bug. Unless someone else can correct me here on "label shorts".... I would say that are meaningless..... If you are DRC and LVS clean (it says schematic and layout match) you should be fine.

Jgk
 

... If you are DRC and LVS clean (it says schematic and layout match) you should be fine.
John is right: it doesn't matter. If you'd like to remove this error message anyway you could smash (1 hierarchy level) one or all these caps and remove one of (or all) their labels.
 

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