effect of sensitivity list on the hardware generated in vhdl

hi
can any one tell me what is the effect of removing the signals from the sensitivity list in a vhdl code. below is the code for it.
intially only signal a is mentioned in the sensitvity list and then later both a and b are mentioned in the sensitivity list. Can any one tell me the diff on c output and the hardware generated in both the cases.
Thanks

entity trial is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic);
end trial;
architecture Behavioral of trial is
begin
process (a)
begin
if (a ='1' and b = '0') or (a = '0' and b = '1' )then
c<= '1';
else
c<= '0';
end if;
end process;
end Behavioral;

Re: effect of sensitivity list on the hardware generated in

s3034585 said:

hi
can any one tell me what is the effect of removing the signals from the sensitivity list in a vhdl code. below is the code for it.
intially only signal a is mentioned in the sensitvity list and then later both a and b are mentioned in the sensitivity list. Can any one tell me the diff on c output and the hardware generated in both the cases.
Thanks

entity trial is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic);
end trial;
architecture Behavioral of trial is
begin
process (a)
begin
if (a ='1' and b = '0') or (a = '0' and b = '1' )then
c<= '1';
else
c<= '0';
end if;
end process;
end Behavioral;

Click to expand...

Theoretically, if you omitting the "b" signal in the sensitivity list, the result is a Latch instead of a Xor.
but attention, not all synthesis tools work at the same way.
Therefore the result not e' sure!

Re: effect of sensitivity list on the hardware generated in

Omitting any signal in the sensitivity list in VHDL results in simulation/synthesis mismatch.. In simulation, u wont get desired results 'coz the process wont trigger when there is an event on the omitted signal...BUT all (read major?) synthesis tools ignore sensitivity list, so u'll get the desired hardware..

tut..

Re: effect of sensitivity list on the hardware generated in

HI ..
VHDL is a in inherent general parallel language .. There are no REGISTER logic primitives . Im order to use the language in a "BEHAVIORAL " abstraction level ... That means to use it to specify behavior of the circuit over time ,We have to "force" sequential statements . In logic synthesis there is a golden rule implemented by the synthesis companies on how to imply "REGISTERED LOGIC ". This is done with the PROCESS STATEMENTS .. the rule goes like this :

PROCESS used for REGISTERED LOGIC
1) write a process that "DOES NOT " include all the inputs in the sensitivity list

2) use incompletly specified "if-the-elsif" ( pay attention to the elsif here)
to imply that one or more signals MUST HOLD THEIR VALUE ( this is the KEY)

3) Use variables in such a way that they hold their value between iterations of the process ..
-----------------------------------------------------------------------------
PROCESS used for COMBINATORIAL LOGIC
1) The sensitivity list includes ALL THE INPUTS

2) the assigment statements written for the PROCESS OUTPUTS
cover all POSSIBLE combinations of the process INPUTS

Re: effect of sensitivity list on the hardware generated in

=> The sensitivity list is a set of signals to which the process is sensitive. Any change in the value of the signals in the sensitivity list will cause immediate execution of the process.If the sensitivity list is not specified, one has to include a wait statement to make sure that the process will halt. Sensitivity list must consist of all signals that are read inside the process.
=> Synthesis is the process of generating circuit/gate level implementations from VHDL model

"Getting Simulation Synthesis Mismatch if sensitivity list not given in process...."

Synthesis tools often ignore sensitivity list, but simulation tools do not…
If proper sensitivity list not specified in process, forgotten signal will lead to difference in behavior of the simulated model
and the synthesized design