Clearing FIFO - whats the difference

Hi,

I was wondering if it there is a difference in implementation when I clear fifo in this way:


and comparing to this approach:


Regards

I don't know about the code, but by nature of fifo, you don't need to clear the contents. Unlike a random access storage, read access to the entry in FIFO takes place after the given entry is written, so that you'll never see those reset values comming out of read port with FIFO(if you see it, something is wrong in the design). So, clearing the contents of FIFO is juse meaningless and a waste of logic, isn't it ?

is it possible to actually implement something like this? A FIFO is a memory and accessing all the 255 elements in one clock cycle is impossible if the FIFO is inferred as RAM in FPGA.
If the FIFO is implemented as a group of individual flip flops then it can be implemented i think. In that case both the codes you have given should do the same thing.
But both these methods will work in a testbench.Am I correct?

--vipin

Both methods do the same thing.
Both methods will result in registers rather than ram being infered when you try and synthesise it.

Advice - never reset a memory.

Thanks for replies!

Correct me if im wrong: it is sufficient to initialize FIFO cleared (filled i.e. with '0' ?) than clearing it in some process?

What's the difference between FIFO resulting in registers than RAM? (and how to write such a FIFOs).

Also I have w question about the titles of books/articles which could explain some main issues about implementation (i.e. how to write more efficient FIFO).

Some synthesisors will accept initialised memory contents. But once this is overwritten you can never reset it (but you shouldnt need to anyway, and with a fifo, why do you want to initialise the contents? if there is no data in the fifo, then the data in the memory is meaningless. There is no reason to set any values in a FIFO ram until you actually write data into it).

if you build a memory from Registers rather than ram, you are likely to see your resources dissapear very quickly. You also will get huge muxes to select the correct output registers for output that will probably fail timing contraints. Apart from the timing problem, you may see your compile times increase a lot. best advice - use ram where you need ram, use registers where you need registers!

Dave_PL said:

Correct me if im wrong: it is sufficient to initialize FIFO cleared (filled i.e. with '0' ?) than clearing it in some process?

Click to expand...

You don't have to initialize it either. When you need to initialize a sequential cell, it is because that is required by the functions, but the data in fifo is just random data which has no functionality by itself. All you need to initialize is a read pointer and write pointer, and maybe some more depending on the design, but contents is usually not required to get reset(unless your fifo is a very special kind that requires the reset).

What's the difference between FIFO resulting in registers than RAM? (and how to write such a FIFOs).

Click to expand...

They are the same in general,, but with ram, the bit lines may get reset at some point in a cycle and may not hold the same value the entire cycle even though the read pointer remains the same, but it depends on ram design.. And with ram, you need to run BIST to test it , while you can run scan test with registers.

Also I have w question about the titles of books/articles which could explain some main issues about implementation (i.e. how to write more efficient FIFO).

Click to expand...

only two things to be careful with fifo. Clock domain crossing of read/write pointers and full/empty condition.

Ive got one more question: is there a difference between FIFO resulting in registers and RAM considering the higher frequency?

Dave_PL said:

Ive got one more question: is there a difference between FIFO resulting in registers and RAM considering the higher frequency?

Click to expand...

Yes - you'll get much better performance out of the ram (unless your fifo is really small). With the registers, it will have to create large output muxes to select the correct register for output. This will create large logic delays.

OK, thanks for enormously fast reply!

But now how to write such a FIFO resulting in RAM?

Just infer a ram, and access it like you do with a fifo.
Rams are infered by having an array of your input data type, and accessing it synchronously. do not reset the array at al and it should just place a ram.

For alteras ram coding style (Xilinx should be similar), see here:
https://www.altera.com/literature/hb/qts/qts_qii51007.pdf