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Clock divider using 4 bit counter on DE2 board (Verilog)

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cse_questions

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I need to convert a 50 MHz / 27 MHz clock to a 1 Hz clock using cascading counters.
I have to use the DE2 board to build a counter of transitions. The counter increments its count at the clock every time the input changes from 1 in the previous cycle to zero in the current cycle. The out- put is the highest bit. The inputs are clock and reset, as usual, and COUNT and INIT. The later has as many bits as the counter has counting flip-flops and is used to initialize the counter every time the counter cycles through. If the counter has three bits, and INIT is two, the counter go through the numbers 2, 3, 4, 5, 6, 7, 2, etc. Using several of these counter modules, none of them with more than four counting bits (i.e. 0-15 max- imum range), create a module that blinks a red LED at 1 Hz.

I thought of ripple counters and I get 0.8 Hz by modulo-25...How do I use INIT to get exactly 1 Hz?
 

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