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Actually I have use this command. and Also I have wirte my own librar too:
library(nand) {
cell(NN2) {
area : 2;
pin(A) {
direction : input;
capacitance : 1;
}
pin(B) {
direction : input;
capacitance : 1;
}
pin(Z) {
direction : output;
function : "A*B";
timing() {
intrinsic_rise : 0.48;
intrinsic_fall : 0.77;
rise_resistance : 0.1443;
fall_resistance : 0.0523;
slope_rise : 0.0;
slope_fall : 0.0;
related_pin : "A";
}
timing() {
intrinsic_rise : 0.48;
intrinsic_fall : 0.77;
rise_resistance : 0.1443;
fall_resistance : 0.0523;
slope_rise : 0.0;
slope_fall : 0.0;
related_pin : "B";
}
}
}
}
then I used read_lib and write_lib to convert to .db format. it was ok until this step. but when I used dc_shell -f x.script it prompt that it needs and, or, nor gate too. and it cannot map my circuit to just nand gate.
but DC prompts :
Error: The target library does not contain all required gates.
Either a NOR, or an AND and an OR gate (two-input) is required for mapping. (OPT-102)
Hi could you let me know why you want to synthesize a combinational logic to only nand or nor gates.
To be honest, I‘ve never try to do so. But, according to ERRORS from DC, I think It means that, DC can not MAP（translate GETCH LIB to STD CELL）only with the cells in the saed90 library do not have the dont_use property.
When synthesizing, DC will translate the HDL description into GETCH(general purpose function STD lib ) structure. Of course there will be some AND OR NOT … logic in the GETCH. that's why the ERRORS come out.
We often dont use "set_dont_use" to disable such tons of STD CELLs.
I usually use it to disable some CLK_BUFs or big_sized delay CELLs, often these CELLs can be replaced by others.
Hello,
Actually all the cells in the library have the dont-use propert except NAND2X0. because I just wanted to map the circuits to just nand gates. thanks
---------- Post added at 14:29 ---------- Previous post was at 14:19 ----------
Hello, I need to do some BILP (binary integer linear programming) thus I need to use just nand gates. theoretically we could built every gates with nand gates. I seems the straight fwd approach is code a script to replace the and-or with nand gates. btw Actually I faced with another problems too. My case study is ISCAS85 benchmarks for example c432.v. after synthesis process I dont get a flat verilog code as attached bellow ( I have my top-module with some different modules for gates)
I wonder if you could suggest a method to force DC to combine those modules to top modules. because in current verison I should do some scripting to read multiinput gates such as and9-1 and put in the my top module (c432) manually . thanks in advance.
module and9_1_1 ( Z, A, B, C, D, E, F, G, H, I );
input A, B, C, D, E, F, G, H, I;
output Z;
wire n1, n2, n3, n4, n5, n6, n7;
Hello,
Actually all the cells in the library have the dont-use propert except NAND2X0. because I just wanted to map the circuits to just nand gates. thanks
---------- Post added at 14:29 ---------- Previous post was at 14:19 ----------
Hello, I need to do some BILP (binary integer linear programming) thus I need to use just nand gates. theoretically we could built every gates with nand gates. I seems the straight fwd approach is code a script to replace the and-or with nand gates. btw Actually I faced with another problems too. My case study is ISCAS85 benchmarks for example c432.v. after synthesis process I dont get a flat verilog code as attached bellow ( I have my top-module with some different modules for gates)
I wonder if you could suggest a method to force DC to combine those modules to top modules. because in current verison I should do some scripting to read multiinput gates such as and9-1 and put in the my top module (c432) manually . thanks in advance.
module and9_1_1 ( Z, A, B, C, D, E, F, G, H, I );
input A, B, C, D, E, F, G, H, I;
output Z;
wire n1, n2, n3, n4, n5, n6, n7;
---------- Post added at 15:47 ---------- Previous post was at 15:13 ----------
hello again.
I have found that with nand+nor+inv set or by and+or_inv set it works. and also these commands:
set_flatten true -design name
compile -ungroup_all
Hello,
Actually all the cells in the library have the dont-use propert except NAND2X0. because I just wanted to map the circuits to just nand gates. thanks
---------- Post added at 14:29 ---------- Previous post was at 14:19 ----------
Hello, I need to do some BILP (binary integer linear programming) thus I need to use just nand gates. theoretically we could built every gates with nand gates. I seems the straight fwd approach is code a script to replace the and-or with nand gates. btw Actually I faced with another problems too. My case study is ISCAS85 benchmarks for example c432.v. after synthesis process I dont get a flat verilog code as attached bellow ( I have my top-module with some different modules for gates)
I wonder if you could suggest a method to force DC to combine those modules to top modules. because in current verison I should do some scripting to read multiinput gates such as and9-1 and put in the my top module (c432) manually . thanks in advance.
module and9_1_1 ( Z, A, B, C, D, E, F, G, H, I );
input A, B, C, D, E, F, G, H, I;
output Z;
wire n1, n2, n3, n4, n5, n6, n7;
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