lyko
Newbie level 2
When the analog design finished, how to generate the "real" model(which means that the models include the real connection pins to the digital, not only arithmetic models) of your analog design for the SOC verification?
As far as I kown, 1 write the models by the designer self using verilog-a(ms).
2 generate the model using some tools? maybe there are.
What is your opinion? thanks.:-?
As far as I kown, 1 write the models by the designer self using verilog-a(ms).
2 generate the model using some tools? maybe there are.
What is your opinion? thanks.:-?
