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Folded cascode concepts......

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samiurrehman

samiurrehman

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Dear all,

1)I am designing a high frequency integrator based on folded cascode topology, but i am a little confused grasping the concepts of folded cascode...e.g the number of transistor stages in cascode structure, biasing, current steering etc...if some one can provide me with some material covering the fundamentals and complexities of folded cascode OTA topology, that would be very kind.

2) for high frequency application which topology is better suited: folded cascode or telescopic?

Regards
 

Hi samiurrehman,

In order to provide you with some answers to your questions,if you don't mind,what it the technology and the power supply available for your design?In addition,what is the frequency of operation of the whole circuit?

Regards,
Jimito13
 

I am using SGB25_dev technology in Cadence, power supply 2.5 V, and frequency operation is 500MHz.

And the real problem is i am really not sure how to extract the magnitude gain from the folded cascode topology??? how it works
 
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Ok,i would suggest those sources (Google them) for folded cascode structure :

CMOS Analog Circuit Design (Allen Holberg)
Structured Analog CMOS Design (Kayal Stefanovic)

With 2.5V power supply you will have no problem to bias the folded cascode circuit.

The frequency of 500MHz refers to the OTA's unity gain frequency?
 

yes we can consider it as unity gain frequency......but can you provide me with some schematics???
 

You will find the desired schematic in the books i suggested to you in my previous post...

Where are you going to use your integrator if you don't mind?
 

Integrator has to be used in delta sigma ADC being designed at our lab for a novel front end to be used in transmitter.
 

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