sebblonline
Newbie level 5
Hi,
Im using the Xilinx XUPV5-LX110t development board and Xilinx ISE 12.1.
I succussfully instantiated the memory controller with MIG and core generator. Now I'm not sure about the clocking of the controller. It has a sys_clk input and a clk200 clock. The connection of the 200MHz clock is clear for me, but i dont know from where to take the sys_clk. Does it have to be the clock Im using in my user logic from where I want to access the RAM? Or does it come from a source outside of the FPGA, because there is also a constraint for this signal.
thanks in advance.
regards,
sebastian
Im using the Xilinx XUPV5-LX110t development board and Xilinx ISE 12.1.
I succussfully instantiated the memory controller with MIG and core generator. Now I'm not sure about the clocking of the controller. It has a sys_clk input and a clk200 clock. The connection of the 200MHz clock is clear for me, but i dont know from where to take the sys_clk. Does it have to be the clock Im using in my user logic from where I want to access the RAM? Or does it come from a source outside of the FPGA, because there is also a constraint for this signal.
thanks in advance.
regards,
sebastian