tanner eda l-edit spr setup

I am using tanner tool 13.i want to generate layout and padframe of a schematic so i export it as tpr file, but how i find suitable library file for standard cell place & route(spr) setup ? i use some example library file that is in tanner library but they give some error such like 'rowcrosser not found' etc.. pls help me .

Salaam.
You need to this file to SPR setup as Standard cells library
Please tell me whether you suceed or not.
Best Regards.
Alireza

I have a problem too.
I extract a system from layout in L-edit. Finally in the extract result, i could not find the inputs and outputs nets of my system. Through a lot of nets and transistors, i could not find proper net to assert proper inputs for testing.

Could you guide me?

thanks for the file. it works now. but this file is for .5 micron mos. if i use .25 micron then ?

Salaam dear Subir
Excuse me for delay in reply.
I think you should by .25 micron technology and it is not included in tanner in advance.
I searched again in Tanner but i only found 0.25 library which related to transistors and other paramaters of technologies and it involved by T-Spice.
Excuse me that i could not help you.
But can i ask you a question?
How could you extract spice netlist from a system layout in 0.5 standard cell library with L-Edit?
Have you ever did this work? If not , How do you do post layout simulation?
Thank you in advance.
Keep in touch please.
Alireza

thats ok, i am telling u what is my prob. and what i am doing:

currently i am using tanner tool v13. often i use s-edit and tspice for simulation purpose and mainly i work on analog circuits i,e CMOS amplifier , opamp etc.

Currently i am designing a cmos opamp for my project. design & T-spice simulation part almost complete. now i have to generate layout. so i search for a layout design tools i.e L-EDIT.
I use S-Edit & T-spice frequenty but i am just a beginer in L-EDIT. when i see SPR (std. cell place & route)feature in L-EDIT, i was interested so that i think i can generate layout of opamp from it. but i able to generate layout of some digital logic like adder,mux etc using it & of course u help me by giving the mhp_n05d.tdb file. but i failed to generate layout of opamp . In my T-spice simulatio by default it take L=0.25 micron & also i use .25 micron library file for simulation

Now my questio is : is it possible to generate layout of opamp or any other analog circuit by using SPR or using another tools or i have to draw it manually which is impossible for me.I If u have any suggestion or idea pls help me

Hi Dear Subir (I think you are a Spanish man, Aren't you?)
I have searched and asked my friends that whether analog circuits layout would be drawn by Auto placement and routing?
I have found in "Bebop to the Boolean Boogie: An Unconventional Guide to Electronics - Third Edition" p 367 says:"LAYOUT (PLACE-AND-ROUTE)
In the case of analog designs at the chip or board level, almost all aspects of layout are performed by hand. Having said this, at the time of this writing, we are seeing some interesting developments with regard to automatic analog placement at the chip level. "

I think it could be done but you should insert your transistor from library mhp_n05 library with correct name and then esport it to .edif file.
I hope it could be a correct flow fo place and route your analog circuit.
Unfortunately i have not enough time to do it myself now and say its result.
I hope it works.
Please inform me of your result.
please keep in touch.
Alireza.

Thanks for your suggestion....i will try it. by the way i am from India