otis
Member level 3
I have a following code
Above is my simplified version of my current code... Original code exactly the same structure.
control goes to case ONE after reset and next_state gets value TWO. Then I expect that on next clock the next_state will get THREE and so on.
But in my case all assignments happens at same clock edge. I means at same edge next_state updated with ONE,TWO,THREE and FOUR. I found this by adding display comment on every case value.
What is wrong?
Code:
module test(clk,out1,out2)
input clk;
output out1,out2;
reg out1,out2;
reg [1:0] next_state;
parameter [1:0] ONE = 2'b00,
TWO = 2'b01,
THREE = 2'b10,
FOUR = 2'b11;
paramter ON = 0,
OFF = 1;
always @ (next_state)
begin
out1 <= next_state[ON];
out2 <= next_state[OFF];
end
always @(posedge clk or posedge rst)
begin
if (posedge rst)
next_state <= ONE;
else
case (next_state)
ONE : next_sate <= TWO;
TWO : next_sate <= THREE;
THREE : next_sate <= FOUR;
FOUR : next_state <= ONE;
endcase
endcontrol goes to case ONE after reset and next_state gets value TWO. Then I expect that on next clock the next_state will get THREE and so on.
But in my case all assignments happens at same clock edge. I means at same edge next_state updated with ONE,TWO,THREE and FOUR. I found this by adding display comment on every case value.
What is wrong?