Bartart
Full Member level 2
ise 6.1 and verilog
Hi friends!!
I have a problem using Xilinx ISE and verilog files, after a synthese I am unable to see a hierarhy in floorplaner. I have check and uncheck the "keep hierarhy" in synthese options menu but still no changes.
Strange is that i don't have any kind of problem if i use vhdl code.
any idea?
thanks bart
Hi friends!!
I have a problem using Xilinx ISE and verilog files, after a synthese I am unable to see a hierarhy in floorplaner. I have check and uncheck the "keep hierarhy" in synthese options menu but still no changes.
Strange is that i don't have any kind of problem if i use vhdl code.
any idea?
thanks bart