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offset current of an opamp

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nnmate

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I´m facing an issue from a textbook which says, for some worst cases, we need an amplifier with offset currents in the 0.01 pA range, (which may be hard to realize?) My question is, how much is a normal offset current for an NMOS Gate input differential amplifier? Is it no other than the gate leakage current?
thanks alot

NN:razz:
 

Thanks Keith, I may want to know, in which range can we reduce the offset current, while designing an opamp. Can we reach the pA range?
 

NNMATE,

I like to remind you that the offset current of a differential amplifier is the DIFFERENCE between both input currents.
This applies for BJT as well as for MOS stages.
 

ye, I know that. Thank you.
So the BJT OP suffers larger offset current at the input stage than the case with CMOS?....
Look forward to your answers LvW and Keith, Thank you again

NN
 

I don't think you will manage 0.01pA input current matching with bipolar!

For CMOS I suspect the protection diodes will be the biggest problem but you would need to look at your process specification. Also, you may need to keep the area of the input transistors small for low bias current (leakage) even though larger would give better matching. I doubt you will get leakage matching process data from the foundry, but I may be wrong.

Keith.
 

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