HMS1021
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ISE 12.2
CPLD: xc2c64
Target Board: Custom
XILINX Platform Cable II USB
Windows 7 / 64
I'm stuck, I appear to execute all steps correctly but I still have no outputs.
Each step in Implement Design is Green and error/warning free. I've written a test bed and it simulates without error and performs as planned. The schematic in Schematic viewer looks correct. I adopted the pin out from the inital Implementation and captured it into my .ucf also setting the I/O STD (LVTTL) and declaring NET CLK BUFG = CLK;
When I click "Configure Target Device" ImPact opens, correctly identifies the device, initializes and programs sucessfully using the .jed file from ISE.. When verify is clicked it comes back OK. The CPLD has no output on any pin as indicated on a Logic analyzer and O'scope.
I scaled the design back to CLK (24MHz 0 - +3.1 V 50% and very square), a single inverter with the inverter output on pin 1. Still no output. I have been at it a week.
Steps to date:
1. Replace inexpensive Digilent USB cable with XILINX programmer, the ease of use and features are better with the XIlinx but still no outputs
2. Based on a Digilent board I changed Vref on the USB programmer and Vaux from 1.8V to 3.2V. The core (Vcc) is 1.79V.
3. Resolved conflict concerrning pull ups on JTAG as seen on older boards. XC2C64 claims internal pull ups and Digilent board does not have them and functions.
4. Searched for hours trying to asscertain role of RST bus on cpld and cpld functioning assumming it may be similar to a /RST on a Ti DSP or similar. My signal 'RSTn' mapped onto global set/reset net GSR and has been set high and low with same result.
5. Replaced the Xc2C64 with a new one.
6. Added a switch to disable free running clock during programming.
I'm sure I'm missing one simple small detail.....
CPLD: xc2c64
Target Board: Custom
XILINX Platform Cable II USB
Windows 7 / 64
I'm stuck, I appear to execute all steps correctly but I still have no outputs.
Each step in Implement Design is Green and error/warning free. I've written a test bed and it simulates without error and performs as planned. The schematic in Schematic viewer looks correct. I adopted the pin out from the inital Implementation and captured it into my .ucf also setting the I/O STD (LVTTL) and declaring NET CLK BUFG = CLK;
When I click "Configure Target Device" ImPact opens, correctly identifies the device, initializes and programs sucessfully using the .jed file from ISE.. When verify is clicked it comes back OK. The CPLD has no output on any pin as indicated on a Logic analyzer and O'scope.
I scaled the design back to CLK (24MHz 0 - +3.1 V 50% and very square), a single inverter with the inverter output on pin 1. Still no output. I have been at it a week.
Steps to date:
1. Replace inexpensive Digilent USB cable with XILINX programmer, the ease of use and features are better with the XIlinx but still no outputs
2. Based on a Digilent board I changed Vref on the USB programmer and Vaux from 1.8V to 3.2V. The core (Vcc) is 1.79V.
3. Resolved conflict concerrning pull ups on JTAG as seen on older boards. XC2C64 claims internal pull ups and Digilent board does not have them and functions.
4. Searched for hours trying to asscertain role of RST bus on cpld and cpld functioning assumming it may be similar to a /RST on a Ti DSP or similar. My signal 'RSTn' mapped onto global set/reset net GSR and has been set high and low with same result.
5. Replaced the Xc2C64 with a new one.
6. Added a switch to disable free running clock during programming.
I'm sure I'm missing one simple small detail.....
