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how to vhdl code for random number generator

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rajeswari01

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how to write vhdl code for random number generator module,which has integer rang 1 to 255,binary 8-bit,number of array equal to 36 ,using function in package "std_logic_unsigned" is conv_integer(arg:std_logic_vector) return integer,i want vhdl code for random number generator module.
 

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First of all, dont use package std_logic_unsigned.
use numeric_std instead.

Second - instead of making us do your work, do your own work yourself and come back when you are stuck
 

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