what is ground pouring?

Hi all
i am planning to use a wireless tranceiver mrf49xa in the datasheet they listed the following :
1- use via filled ground patch underneath the IC
2- surrond the clock with an adjacant ground pour


what are these ? do they mean simply a route( line) connected to ground

sorry i am new to RF and pcb :sad:
but eager to learn 8-O

thanks

Ground pouring refers to placing a shape of copper tied to the net "Ground".

Some app notes and spec sheets refer to this when they want you to provide shielding just beneath the part. other times it is used to mitigate thermal issues by actually soldering the bottom of the part to a large copper area or using thermal tape or glue to contact the bottom of the part to this copper area. Ground pouring might be referred to in your ECAD tool as Area fill or plane (usually positive).

If you are using the ground pour (fill) beneath the part and they expect you to be soldering to it, be sure to include a soldermask and solderpaste opening beneath the part in the shape of the conductive underside of the part. also place vias in this area and be sure the board fabricator knows to fill them with conductive material, otherwise your paste will heat up and run down the vias.

for surrounding a trace with ground pour, they want you to encase the length of the trace with a guard net of ground. you can do this with an Area fill (ground pour) with vias tying it your ground plane or in if your ECAD tool has a shield command, you can use that.

1- use via filled ground patch underneath the IC
---This is for Thermal requirements of the IC. The Center pad of the IC has to be soldered on the Board so You have to provide a Ground patch and open the Mask for the shape and also Provide Solder Paste it the assembly is automatic. You can duplicate the copper shape on the bottom side to provide more thermal dissipation.

2- surround the clock with an adjacent ground pour.
A clock signal is a high switching signal ( rate of switching depends on the frequency of Clock) and also a critical signal in the design. Its recommended to Guard the clock with GND trace with GND vias at a regular distance. Or else you can Pour copper ( Create a PLANE).

mashak said:

Its recommended to Guard the clock with GND trace with GND vias at a regular distance. Or else you can Pour copper ( Create a PLANE).

Click to expand...

Dear Mashak.....Can you please specify the method for determining distance between Trace and Ground pour?
Is there any rule of thumb for it?

MW_Engineer said:

Dear Mashak.....Can you please specify the method for determining distance between Trace and Ground pour?
Is there any rule of thumb for it?

Click to expand...

Usually, at a minimum, you must respect the finest geometry that your board fabrication house can produce. Although your RS-274 (photo plot) file may have certain minimum widths, the board fabricator has physical processes that usually dictate the minimum feature size, including spacing between traces. If voltage breakdown, or maintaining enough spacing from HV 'creep' between conductors is not a concern, the next concern might be EM coupling from adjacent traces.

The designer must have some sense of what is required from several perspectives.

Jim

When you are starting out, one of the best sources of information and answers for a design based on a paticular device, is an evaluation board:
https://ww1.microchip.com/downloads/en/DeviceDoc/51843A.pdf
Then when you get old and experienced, the best way of getting a job done with the minimum of hassle is to copy the eval board.:grin:
There is a lot more involbed, quite often vias under various devices are there as "Thermal Vias", do a search on thermal vias and QFN packages.