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[SOLVED] VerilogA - simple error and confusion

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starsunmoon

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((Question on Verilog-A . Please feel free to move to a more proper board if there is one: ))

How to assign a value to an element of an array ?

what I have by following an example from cad tool's example:

......

input vin;
electrical vin;
parameter real vd[0:7] = '{0,0,0,0,0,0,0,0};

analog begin

if (V(vin)==1) vd[0] = '{3.3};

end

......


The error message I got is:



ERROR (VACOMP-1567): "if (V(vin)==1) vd[0] = '{3.3};<<--? "
"~/block1/veriloga/veriloga.va",
line 26: Encountered assignment to a parameter in an incorrect context.
Assign parameters only in the same statement in which you declare
them.
 

You cannot assign a value to a parameter within the analog block. Try to define vd as a real only (not parameter real but just real).
 
I changed the code as said, and it helped to eliminate that error. So I tried to initialize the array element following the toolkit example using "generate", and however got the following errors. Wondering if you could tell the correct syntax to complete this array element initialization and later on read-write. Thank you !



generate i (7, 0) begin
vd = 0;
end



Error found by spectre during AHDL compile.
ERROR (VACOMP-2259): "generate<<--? i (7, 0) begin"
"~/block1/veriloga/veriloga.va",
line 20: syntax error.
ERROR (VACOMP-1814): Maximum allowable errors exceeded. Exiting AHDL
compilation....
 
Last edited:

If vd is defined ad real vd[7:0], you can initialize it as:
Code:
for (i=0;i<=7;i=i+1)
vd[i]=0.0;
The generate statement applies only to output quantities.
 

Thanks a lot. However, after putting in those code, it complained about the 'for' loop. It is "syntax error" though no further explaination given.
 

I do not see any syntax error in the line I sent you. Maybe you want to show the whole code to get some help?
 
... it complained about the 'for' loop. It is "syntax error" though no further explaination given.
May be you missed the begin & end statements in your for loop? See e.g. **broken link removed**, p. 31 bottom (p. 47 of the PDF).
 
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