vlsi_mani
Newbie level 1
I have an SV interface definition. (Used both inside RTL as well as test bench top) (PS: this is only a tiny bit of the entire code)
interface bus_if(input clk, rst_n);
`include "bus_params.v"
logic [3:0] cfg_slave[0:1];
modport slave_port(input clk,rst_n,cfg_slave);
modport master_port(input clk,rst_n,output cfg_slave);
endinterface
-------------
The signal gets driven from a verilog module. There are also some VHDL modules - but they don't directly talk to the interface.
Though this signal has been declared in modport, DC complains of a ref port in the instantiation.
When I synthesis the SV code alone separately, there is no issue.
So it appears more like mixed signal driving issue.
When I change the logic data type to wire the errors go away - but that is not the right way to do it(since erroneous multiple driving cannot be detected and also DC might infer tristate logic even otherwise)
Has anybody tried using interface modports with verilog and vhdl sources... is it synthesisable w/o issues ?
interface bus_if(input clk, rst_n);
`include "bus_params.v"
logic [3:0] cfg_slave[0:1];
modport slave_port(input clk,rst_n,cfg_slave);
modport master_port(input clk,rst_n,output cfg_slave);
endinterface
-------------
The signal gets driven from a verilog module. There are also some VHDL modules - but they don't directly talk to the interface.
Though this signal has been declared in modport, DC complains of a ref port in the instantiation.
When I synthesis the SV code alone separately, there is no issue.
So it appears more like mixed signal driving issue.
When I change the logic data type to wire the errors go away - but that is not the right way to do it(since erroneous multiple driving cannot be detected and also DC might infer tristate logic even otherwise)
Has anybody tried using interface modports with verilog and vhdl sources... is it synthesisable w/o issues ?