PLL Question, Can the duty cycle be trimmed, while keeping its frequency locked?

Hello all,

I have a question, When using a High precision PLL and it is locked into its frequency could it then be further adjusted to change its duty cycle? Or is it always 50%?

I only ask because I want to trigger an event on its rising edge and then another on its falling edge. But i would need it to an exact 50% duty cycle so if possible i might need to trim to 50% over process, temp, blah blah.....

Is this possible or is it always whatever it is born at?

JGK

To be on the safe side, you could (perhaps) create double the frequency, then divide by 2 ?

That is a good idea but I can't do that. Is it possible to trim the duty cycle of a PLL while keeping its frequency the same?

jgk2004 said:

Is it possible to trim the duty cycle of a PLL while keeping its frequency the same?

Click to expand...

I wouldn't think so: a PLL is a closed-loop control system. If you intervene by any kind of additional control measure, you'll probably interfere considerably with the proper PLL control function.

But as it is a phase-locked system, by holding the reference signal stiffly at 50% duty cycle, there's a good chance that the output signal will do as well - during lock, of course.

Thanks Erikl, I am then going to try to build some type to trim which also triggers off the rising edge and I can delays it into 50%. do you think this is a good idea?

jgk2004 said:

I am then going to try to build some type to trim which also triggers off the rising edge and I can delays it into 50%. do you think this is a good idea?

Click to expand...

Yes, john, I think so. May be the phase ratio isn't necessarily 1:1 , the phases may be delayed - but still locked. You better keep your ref signal duty cycle (or the trigger point) adjustable.
PS: Still see chichi? R'gards, if so!

In contrast to what's been said before, I'm sure, that the duty cycle is an independant parameter of the VCO. It isn't controlled by the PLL and does not (or only slightly) influence it's operation. The exact answer depends on the phase detector design. Particularly, the VCO duty cycle doesn't depend on the reference input's duty cycle.

With most VCOs, e.g. differential ring oscillators, that are popular for a wide frequency range of 100 MHz up to several GHz, the output waveform can be expected almost symmetrical. But built-in unsymmetries may change it from ideal 50% duty cycle. I haven't seen yet oscillator designs with additional duty cycle control input, but I think, it could be done if actually required. Alternatively, you can apply pulse shaping to the VCO output signal.

You could take the output of the VCO, run it through
some comparator type deal (perhaps an ECL or CML
gate would do if high speed), low pass filter the output
and feed that to an op amp with the average of VIH and
VIL as a reference, and use that op amp loop to feed the
other input of the front end comparator / gate. This will
seek 50% duty cycle.

But of course the fly in this ointment is that you'll likely
add a whole bunch of phase noise after the PLL.

I suspect there are many ways to do this. for example, two phases (or more) from a ring oscillator could be used with an AND gate to generate pulses that are between 25% and 50% duty ratio. One pulse could go to a controllable delay line, the other could go to a fixed delay line (or no delay). the OR of these two signals will produce a pulse between D and 2D by adjusting the delay. degenerate cases for 0Hz, runt pulses, and clock doubling exist if the tuning range is made high enough.

of course this pulse would not be phase locked unless it was used with the PFD in the PLL's control loop. This method would require the control loop be able to accept the AND/OR gate delay on the output of the open-loop VCO.

a second, independent control loop would then be needed to calibrate the duty ratio over process/temperature. Depending on the full dynamics of the system, some dither based on expected subharmonics might be required. For non-fixed frequency operation, some injection of the change in Vco control input might be required, as the duty ratio loop would not be able to respond to a change in frequency until it actually happens. injection of a "change in frequency" signal might allow the duty ratio to stay closer to 50% duty ratio when tracking transients.

I'm sure there are many other ways.

jgk2004 said:

Hello all,

I have a question, When using a High precision PLL and it is locked into its frequency could it then be further adjusted to change its duty cycle? Or is it always 50%?

I only ask because I want to trigger an event on its rising edge and then another on its falling edge. But i would need it to an exact 50% duty cycle so if possible i might need to trim to 50% over process, temp, blah blah.....

Is this possible or is it always whatever it is born at?

JGK

Click to expand...

Can the duty cycle be trimmed

Click to expand...

Which duty cycle???
I assume VCO's output
For 4046 PLL at VCO :
replace capacitor between pins 6 -||- 7 with two capacitors , first connected from pin 6 to GND , secondary connected from pin 7 to GND
( add trimmer or varicap in parallel with one of them,or both, to adjust)
Sorry for my english

A auto calibration circuit can be employed for 50% duty cycle correction. The principal is similar to the chargepump in PLL. The on time is used to charge while the off time is used to discharge. The output voltage of chargepump can be used for the edge delay controlling. This feedback loop will calibrate the duty cycle.